isa/rv64mi/breakpoint.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # breakpoint.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test breakpoints, if they are implemented.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Set up breakpoint to trap on M-mode fetches.
  17   li TESTNUM, 2
  18
  19   # Skip tdrselect if hard-wired.
  20   li a0, 1<<(_RISCV_SZLONG-1)
  21   csrw tdrselect, a0
  22   csrr a1, tdrselect
  23   bne a0, a1, pass
  24
  25   # Make sure there's a breakpoint there.
  26   csrr a0, tdrdata1
  27   srli a0, a0, _RISCV_SZLONG-4
  28   li a1, 1
  29   bne a0, a1, pass
  30
  31   la a2, 1f
  32   csrw tdrdata2, a2
  33   li a0, BPCONTROL_M | BPCONTROL_X
  34   csrw tdrdata1, a0
  35   # Skip if breakpoint type is unsupported.
  36   csrr a1, tdrdata1
  37   andi a1, a1, 0x7ff
  38   bne a0, a1, 2f
  39   .align 2
  40 1:
  41   # Trap handler should skip this instruction.
  42   beqz x0, fail
  43
  44   # Make sure reads don't trap.
  45   li TESTNUM, 3
  46   lw a0, (a2)
  47
  48 2:
  49   # Set up breakpoint to trap on M-mode reads.
  50   li TESTNUM, 4
  51   li a0, BPCONTROL_M | BPCONTROL_R
  52   csrw tdrdata1, a0
  53   # Skip if breakpoint type is unsupported.
  54   csrr a1, tdrdata1
  55   andi a1, a1, 0x7ff
  56   bne a0, a1, 2f
  57   la a2, data1
  58   csrw tdrdata2, a2
  59
  60   # Trap handler should skip this instruction.
  61   lw a2, (a2)
  62   beqz a2, fail
  63
  64   # Make sure writes don't trap.
  65   li TESTNUM, 5
  66   sw x0, (a2)
  67
  68 2:
  69   # Set up breakpoint to trap on M-mode stores.
  70   li TESTNUM, 6
  71   li a0, BPCONTROL_M | BPCONTROL_W
  72   csrw tdrdata1, a0
  73   # Skip if breakpoint type is unsupported.
  74   csrr a1, tdrdata1
  75   andi a1, a1, 0x7ff
  76   bne a0, a1, 2f
  77
  78   # Trap handler should skip this instruction.
  79   sw a2, (a2)
  80
  81   # Make sure store didn't succeed.
  82   li TESTNUM, 7
  83   lw a2, (a2)
  84   bnez a2, fail
  85
  86   # Try to set up a second breakpoint.
  87   li a0, (1<<(_RISCV_SZLONG-1)) + 1
  88   csrw tdrselect, a0
  89   csrr a1, tdrselect
  90   bne a0, a1, pass
  91
  92   # Make sure there's a breakpoint there.
  93   csrr a0, tdrdata1
  94   srli a0, a0, _RISCV_SZLONG-4
  95   li a1, 1
  96   bne a0, a1, pass
  97
  98   li a0, BPCONTROL_M | BPCONTROL_R
  99   csrw tdrdata1, a0
 100   la a3, data2
 101   csrw tdrdata2, a3
 102
 103   # Make sure the second breakpoint triggers.
 104   li TESTNUM, 8
 105   lw a3, (a3)
 106   beqz a3, fail
 107
 108   # Make sure the first breakpoint still triggers.
 109   li TESTNUM, 10
 110   la a2, data1
 111   sw a2, (a2)
 112   li TESTNUM, 11
 113   lw a2, (a2)
 114   bnez a2, fail
 115
 116 2:
 117   TEST_PASSFAIL
 118
 119 mtvec_handler:
 120   # Only even-numbered tests should trap.
 121   andi t0, TESTNUM, 1
 122   bnez t0, fail
 123
 124   li t0, CAUSE_BREAKPOINT
 125   csrr t1, mcause
 126   bne t0, t1, fail
 127
 128   csrr t0, mepc
 129   addi t0, t0, 4
 130   csrw mepc, t0
 131   mret
 132
 133 RVTEST_CODE_END
 134
 135   .data
 136 RVTEST_DATA_BEGIN
 137
 138   TEST_DATA
 139
 140 data1: .word 0
 141 data2: .word 0
 142
 143 RVTEST_DATA_END