73d6c6c598df7ea6224c8d5435279458762bb9d5
[riscv-tests.git] / isa / rv64mi / dirty.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # dirty.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test VM referenced and dirty bits.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64M
14 RVTEST_CODE_BEGIN
15
16 # Turn on VM with superpage identity mapping
17 la a1, page_table_1
18 srl a1, a1, RISCV_PGSHIFT
19 csrw sptbr, a1
20 sfence.vm
21 li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
22 csrs mstatus, a1
23 la a1, 1f
24 csrw mepc, a1
25 eret
26 1:
27
28 # Try a faulting store to make sure dirty bit is not set
29 li TESTNUM, 2
30 li t0, 1
31 sw t0, dummy, t1
32
33 # Load new page table
34 li TESTNUM, 3
35 la t0, page_table_2
36 srl t0, t0, RISCV_PGSHIFT
37 csrw sptbr, t0
38 sfence.vm
39
40 # Try a non-faulting store to make sure dirty bit is set
41 sw t0, dummy, t1
42
43 # Make sure R and D bits are set
44 lw t0, page_table_2
45 li t1, PTE_R | PTE_D
46 and t0, t0, t1
47 bne t0, t1, die
48
49 RVTEST_PASS
50
51 TEST_PASSFAIL
52
53 stvec_handler:
54 csrr t0, scause
55 li t1, 2
56 bne TESTNUM, t1, 1f
57 # Make sure R bit is set
58 lw t0, page_table_1
59 li t1, PTE_R
60 and t0, t0, t1
61 bne t0, t1, die
62
63 # Make sure D bit is clear
64 lw t0, page_table_1
65 li t1, PTE_D
66 and t0, t0, t1
67 beq t0, t1, die
68
69 csrr t0, sepc
70 add t0, t0, 4
71 csrw sepc, t0
72 sret
73
74 die:
75 RVTEST_FAIL
76
77 .data
78 .align 12
79 page_table_1: .dword PTE_V | PTE_TYPE_URX_SRX
80 dummy: .dword 0
81 .align 12
82 page_table_2: .dword PTE_V | PTE_TYPE_URWX_SRWX
83
84 RVTEST_CODE_END