isa/rv64mi/dirty.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # dirty.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test VM referenced and dirty bits.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Turn on VM with superpage identity mapping
  17   la a1, page_table_1
  18   srl a1, a1, RISCV_PGSHIFT
  19   la a2, page_table_2
  20   srl a2, a2, RISCV_PGSHIFT
  21   csrw sptbr, a1
  22   sfence.vm
  23   li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
  24   csrs mstatus, a1
  25   la a1, 1f - DRAM_BASE
  26   csrw mepc, a1
  27   la a1, stvec_handler - DRAM_BASE
  28   csrw stvec, a1
  29   mret
  30 1:
  31
  32   # Try a faulting store to make sure dirty bit is not set
  33   li TESTNUM, 2
  34   li t0, 1
  35   sw t0, dummy, t1
  36
  37   # Load new page table
  38   li TESTNUM, 3
  39   csrw sptbr, a2
  40   sfence.vm
  41
  42   # Try a non-faulting store to make sure dirty bit is set
  43   sw t0, dummy, t1
  44
  45   # Make sure R and D bits are set
  46   lw t0, page_table_2
  47   li t1, PTE_R | PTE_D
  48   and t0, t0, t1
  49   bne t0, t1, die
  50
  51   RVTEST_PASS
  52
  53   TEST_PASSFAIL
  54
  55 stvec_handler:
  56   csrr t0, scause
  57   li t1, 2
  58   bne TESTNUM, t1, 1f
  59   # Make sure R bit is set
  60   lw t0, page_table_1
  61   li t1, PTE_R
  62   and t0, t0, t1
  63   bne t0, t1, die
  64
  65   # Make sure D bit is clear
  66   lw t0, page_table_1
  67   li t1, PTE_D
  68   and t0, t0, t1
  69   beq t0, t1, die
  70
  71   csrr t0, sepc
  72   add t0, t0, 4
  73   csrw sepc, t0
  74   sret
  75
  76 die:
  77   RVTEST_FAIL
  78
  79 RVTEST_CODE_END
  80
  81   .data
  82 RVTEST_DATA_BEGIN
  83
  84   TEST_DATA
  85
  86 .align 12
  87 page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URX_SRX
  88 dummy: .dword 0
  89 .align 12
  90 page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URWX_SRWX
  91
  92 RVTEST_DATA_END