isa/rv64mi/dirty.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # dirty.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test VM referenced and dirty bits.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Turn on VM with superpage identity mapping
  17   la a1, page_table_1
  18   csrw sptbr, a1
  19   sfence.vm
  20   li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV43) | ((MSTATUS_PRV1 & ~(MSTATUS_PRV1<<1)) * PRV_S)
  21   csrs mstatus, a1
  22   la a1, 1f
  23   csrw mepc, a1
  24   eret
  25 1:
  26
  27   # Try a faulting store to make sure dirty bit is not set
  28   li TESTNUM, 2
  29   li t0, 1
  30   sd t0, dummy, t1
  31
  32   # Load new page table
  33   li TESTNUM, 3
  34   la t0, page_table_2
  35   csrw sptbr, t0
  36   sfence.vm
  37
  38   # Try a non-faulting store to make sure dirty bit is set
  39   sd t0, dummy, t1
  40
  41   # Make sure R and D bits are set
  42   lw t0, page_table_2
  43   li t1, PTE_R | PTE_D
  44   and t0, t0, t1
  45   bne t0, t1, die
  46
  47   RVTEST_PASS
  48
  49   TEST_PASSFAIL
  50
  51 stvec_handler:
  52   csrr t0, scause
  53   li t1, 2
  54   bne TESTNUM, t1, 1f
  55   # Make sure R bit is set
  56   lw t0, page_table_1
  57   li t1, PTE_R
  58   and t0, t0, t1
  59   bne t0, t1, die
  60
  61   # Make sure D bit is clear
  62   lw t0, page_table_1
  63   li t1, PTE_D
  64   and t0, t0, t1
  65   beq t0, t1, die
  66
  67   csrr t0, sepc
  68   add t0, t0, 4
  69   csrw sepc, t0
  70   sret
  71
  72 die:
  73   RVTEST_FAIL
  74
  75 .data
  76 .align 13
  77 page_table_1: .dword PTE_V | PTE_SX | PTE_SR
  78 dummy: .dword 0
  79 .align 13
  80 page_table_2: .dword PTE_V | PTE_SX | PTE_SR | PTE_SW
  81
  82 RVTEST_CODE_END