isa/rv64mi/illegal.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # illegal.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test illegal instruction trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   .align 2
  17   .option norvc
  18
  19   li TESTNUM, 2
  20 bad2:
  21   .word 0
  22   j fail
  23
  24   # Test vectored interrupts if they are supported.
  25 test_vectored_interrupts:
  26   csrwi mip, MIP_SSIP
  27   csrwi mie, MIP_SSIP
  28   la t0, mtvec_handler + 1
  29   csrrw s0, mtvec, t0
  30   csrr t0, mtvec
  31   andi t0, t0, 1
  32   beqz t0, msip
  33   csrsi mstatus, MSTATUS_MIE
  34 1:
  35   j 1b
  36
  37 msip:
  38   csrw mtvec, s0
  39
  40   # Skip the rest of the test if S-mode is not present.
  41   li t0, MSTATUS_MPP
  42   csrc mstatus, t0
  43   li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
  44   csrs mstatus, t1
  45   csrr t2, mstatus
  46   and t2, t2, t0
  47   bne t1, t2, pass
  48
  49   # Delegate supervisor software interrupts so WFI won't stall.
  50   csrwi mideleg, MIP_SSIP
  51   la t0, 1f
  52   csrw mepc, t0
  53   mret
  54
  55 1:
  56   # Make sure WFI doesn't trap when TW=0.
  57   wfi
  58 bad3:
  59   .word 0
  60   j fail
  61
  62 bad4:
  63   # Make sure WFI does trap when TW=1.
  64   wfi
  65   j fail
  66
  67   # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
  68   sfence.vma
  69   csrr t0, sptbr
  70 bad5:
  71   .word 0
  72   j fail
  73
  74 bad6:
  75   # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
  76   sfence.vma
  77   j fail
  78 bad7:
  79   csrr t0, sptbr
  80   j fail
  81
  82   # Make sure SRET doesn't trap when TSR=0.
  83   la t0, bad8
  84   csrw sepc, t0
  85   li t0, SSTATUS_SPP
  86   csrs sstatus, t0
  87   li t0, SSTATUS_SPIE
  88   csrc sstatus, t0
  89   sret
  90 bad8:
  91   .word 0
  92   j fail
  93
  94   # Make sure SRET does trap when TSR=1.
  95   la t0, 1f
  96   csrw sepc, t0
  97 bad9:
  98   sret
  99 1:
 100   j fail
 101
 102   TEST_PASSFAIL
 103
 104   .align 8
 105 mtvec_handler:
 106   j synchronous_exception
 107   j msip
 108   j fail
 109   j fail
 110   j fail
 111   j fail
 112   j fail
 113   j fail
 114   j fail
 115   j fail
 116   j fail
 117   j fail
 118   j fail
 119   j fail
 120   j fail
 121   j fail
 122
 123 synchronous_exception:
 124   li t1, CAUSE_ILLEGAL_INSTRUCTION
 125   csrr t0, mcause
 126   bne t0, t1, fail
 127   csrr t0, mepc
 128   la t1, bad2
 129   beq t0, t1, 2f
 130   la t1, bad3
 131   beq t0, t1, 3f
 132   la t1, bad4
 133   beq t0, t1, 4f
 134   la t1, bad5
 135   beq t0, t1, 5f
 136   la t1, bad6
 137   beq t0, t1, 6f
 138   la t1, bad7
 139   beq t0, t1, 7f
 140   la t1, bad8
 141   beq t0, t1, 8f
 142   la t1, bad9
 143   beq t0, t1, 9f
 144   j fail
 145 2:
 146 4:
 147 6:
 148 7:
 149   addi t0, t0, 8
 150   csrw mepc, t0
 151   mret
 152
 153 3:
 154   li t1, MSTATUS_TW
 155   csrs mstatus, t1
 156   j 2b
 157
 158 5:
 159   li t1, MSTATUS_TVM
 160   csrs mstatus, t1
 161   j 2b
 162
 163 8:
 164   li t1, MSTATUS_TSR
 165   csrs mstatus, t1
 166   j 2b
 167
 168 9:
 169   j 2b
 170
 171 RVTEST_CODE_END
 172
 173   .data
 174 RVTEST_DATA_BEGIN
 175
 176   TEST_DATA
 177
 178 RVTEST_DATA_END