isa/rv64mi/illegal.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # illegal.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test illegal instruction trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   li TESTNUM, 2
  17 bad2:
  18   .word 0
  19   j fail
  20
  21   # Skip the rest of the test if S-mode is not present.
  22   li t0, MSTATUS_MPIE
  23   csrc mstatus, t0
  24   li t0, MSTATUS_MPP
  25   csrc mstatus, t0
  26   li t1, (MSTATUS_MPP & ~(MSTATUS_MPP << 1)) * PRV_S
  27   csrs mstatus, t1
  28   csrr t2, mstatus
  29   and t2, t2, t0
  30   bne t1, t2, pass
  31
  32   # Set a software interrupt pending so WFI won't stall.
  33   csrwi mideleg, MIP_SSIP
  34   csrwi mip, MIP_SSIP
  35   csrwi mie, MIP_SSIP
  36   la t0, 1f
  37   csrw mepc, t0
  38   mret
  39
  40 1:
  41   # Make sure WFI doesn't trap when TW=0.
  42   wfi
  43 bad3:
  44   .word 0
  45   j fail
  46
  47 bad4:
  48   # Make sure WFI does trap when TW=1.
  49   wfi
  50   j fail
  51
  52   # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
  53   sfence.vma
  54   csrr t0, sptbr
  55 bad5:
  56   .word 0
  57   j fail
  58
  59 bad6:
  60   # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
  61   sfence.vma
  62   j fail
  63 bad7:
  64   csrr t0, sptbr
  65   j fail
  66
  67   # Make sure SRET doesn't trap when TSR=0.
  68   la t0, bad8
  69   csrw sepc, t0
  70   li t0, SSTATUS_SPP
  71   csrs sstatus, t0
  72   li t0, SSTATUS_SPIE
  73   csrc sstatus, t0
  74   sret
  75 bad8:
  76   .word 0
  77   j fail
  78
  79   # Make sure SRET does trap when TSR=1.
  80   la t0, 1f
  81   csrw sepc, t0
  82 bad9:
  83   sret
  84 1:
  85   j fail
  86
  87   TEST_PASSFAIL
  88
  89 mtvec_handler:
  90   li t1, CAUSE_ILLEGAL_INSTRUCTION
  91   csrr t0, mcause
  92   bne t0, t1, fail
  93   csrr t0, mepc
  94   la t1, bad2
  95   beq t0, t1, 2f
  96   la t1, bad3
  97   beq t0, t1, 3f
  98   la t1, bad4
  99   beq t0, t1, 4f
 100   la t1, bad5
 101   beq t0, t1, 5f
 102   la t1, bad6
 103   beq t0, t1, 6f
 104   la t1, bad7
 105   beq t0, t1, 7f
 106   la t1, bad8
 107   beq t0, t1, 8f
 108   la t1, bad9
 109   beq t0, t1, 9f
 110   j fail
 111 2:
 112 4:
 113 6:
 114 7:
 115   addi t0, t0, 8
 116   csrw mepc, t0
 117   mret
 118
 119 3:
 120   li t1, MSTATUS_TW
 121   csrs mstatus, t1
 122   j 2b
 123
 124 5:
 125   li t1, MSTATUS_TVM
 126   csrs mstatus, t1
 127   j 2b
 128
 129 8:
 130   li t1, MSTATUS_TSR
 131   csrs mstatus, t1
 132   j 2b
 133
 134 9:
 135   j pass
 136
 137 RVTEST_CODE_END
 138
 139   .data
 140 RVTEST_DATA_BEGIN
 141
 142   TEST_DATA
 143
 144 RVTEST_DATA_END