a1b445f0df08c7b3b47ab9b9fe41d62f4e115d08
[riscv-tests.git] / isa / rv64mi / illegal.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal instruction trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64M
14 RVTEST_CODE_BEGIN
15
16 .align 2
17 .option norvc
18
19 li TESTNUM, 2
20 bad2:
21 .word 0
22 j fail
23
24 # Skip the rest of the test if S-mode is not present.
25 li t0, MSTATUS_MPP
26 csrc mstatus, t0
27 li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
28 csrs mstatus, t1
29 csrr t2, mstatus
30 and t2, t2, t0
31 bne t1, t2, pass
32
33 # Test vectored interrupts if they are supported.
34 test_vectored_interrupts:
35 csrwi mip, MIP_SSIP
36 csrwi mie, MIP_SSIP
37 la t0, mtvec_handler + 1
38 csrrw s0, mtvec, t0
39 csrr t0, mtvec
40 andi t0, t0, 1
41 beqz t0, msip
42 csrsi mstatus, MSTATUS_MIE
43 1:
44 j 1b
45 msip:
46 csrw mtvec, s0
47
48 # Delegate supervisor software interrupts so WFI won't stall.
49 csrwi mideleg, MIP_SSIP
50 # Enter supervisor mode.
51 la t0, 1f
52 csrw mepc, t0
53 li t0, MSTATUS_MPP
54 csrc mstatus, t0
55 li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
56 csrs mstatus, t1
57 mret
58
59 1:
60 # Make sure WFI doesn't trap when TW=0.
61 wfi
62 bad3:
63 .word 0
64 j fail
65
66 bad4:
67 # Make sure WFI does trap when TW=1.
68 wfi
69 j fail
70
71 # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
72 sfence.vma
73 csrr t0, sptbr
74 bad5:
75 .word 0
76 j fail
77
78 bad6:
79 # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
80 sfence.vma
81 j fail
82 bad7:
83 csrr t0, sptbr
84 j fail
85
86 # Make sure SRET doesn't trap when TSR=0.
87 la t0, bad8
88 csrw sepc, t0
89 li t0, SSTATUS_SPP
90 csrs sstatus, t0
91 li t0, SSTATUS_SPIE
92 csrc sstatus, t0
93 sret
94 bad8:
95 .word 0
96 j fail
97
98 # Make sure SRET does trap when TSR=1.
99 la t0, 1f
100 csrw sepc, t0
101 bad9:
102 sret
103 1:
104 j fail
105
106 TEST_PASSFAIL
107
108 .align 8
109 mtvec_handler:
110 j synchronous_exception
111 j msip
112 j fail
113 j fail
114 j fail
115 j fail
116 j fail
117 j fail
118 j fail
119 j fail
120 j fail
121 j fail
122 j fail
123 j fail
124 j fail
125 j fail
126
127 synchronous_exception:
128 li t1, CAUSE_ILLEGAL_INSTRUCTION
129 csrr t0, mcause
130 bne t0, t1, fail
131 csrr t0, mepc
132 la t1, bad2
133 beq t0, t1, 2f
134 la t1, bad3
135 beq t0, t1, 3f
136 la t1, bad4
137 beq t0, t1, 4f
138 la t1, bad5
139 beq t0, t1, 5f
140 la t1, bad6
141 beq t0, t1, 6f
142 la t1, bad7
143 beq t0, t1, 7f
144 la t1, bad8
145 beq t0, t1, 8f
146 la t1, bad9
147 beq t0, t1, 9f
148 j fail
149 2:
150 4:
151 6:
152 7:
153 addi t0, t0, 8
154 csrw mepc, t0
155 mret
156
157 3:
158 li t1, MSTATUS_TW
159 csrs mstatus, t1
160 j 2b
161
162 5:
163 li t1, MSTATUS_TVM
164 csrs mstatus, t1
165 j 2b
166
167 8:
168 li t1, MSTATUS_TSR
169 csrs mstatus, t1
170 j 2b
171
172 9:
173 j 2b
174
175 RVTEST_CODE_END
176
177 .data
178 RVTEST_DATA_BEGIN
179
180 TEST_DATA
181
182 RVTEST_DATA_END