Pass newly updated -march, -mabi options to gcc
[riscv-tests.git] / isa / rv64mi / ipi.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ipi.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test interprocessor interrupts.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64M
14 RVTEST_CODE_BEGIN
15
16 # enable interrupts
17 csrs mstatus, MSTATUS_MIE
18 csrs mie, MIP_MSIP
19
20 # get a unique core id
21 la a0, coreid
22 li a1, 1
23 amoadd.w a2, a1, (a0)
24
25 # for now, only run this on core 0
26 1:li a3, 1
27 bgeu a2, a3, 1b
28
29 # send a self-IPI
30 csrwi mipi, 1
31 1: j 1b
32
33 mtvec_handler:
34 bnez a2, fail
35 RVTEST_PASS
36
37 TEST_PASSFAIL
38
39 RVTEST_CODE_END
40
41 .data
42 RVTEST_DATA_BEGIN
43
44 TEST_DATA
45
46 coreid: .word 0
47 foo: .word 0
48
49 RVTEST_DATA_END