isa/rv64mi/ma_addr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_addr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ld/st trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   .option norvc
  17
  18   la s0, data
  19
  20   # indicate it's a load test
  21   li s1, CAUSE_MISALIGNED_LOAD
  22
  23 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
  24   li TESTNUM, testnum; \
  25   addi t1, base, offset; \
  26   insn x0, offset(base); \
  27   j fail \
  28
  29   MISALIGNED_LDST_TEST(2,  lh,  s0, 1)
  30   MISALIGNED_LDST_TEST(3,  lhu, s0, 1)
  31   MISALIGNED_LDST_TEST(4,  lw,  s0, 1)
  32   MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
  33   MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
  34
  35 #if __riscv_xlen == 64
  36   MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
  37   MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
  38   MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
  39
  40   MISALIGNED_LDST_TEST(10, ld, s0, 1)
  41   MISALIGNED_LDST_TEST(11, ld, s0, 2)
  42   MISALIGNED_LDST_TEST(12, ld, s0, 3)
  43   MISALIGNED_LDST_TEST(13, ld, s0, 4)
  44   MISALIGNED_LDST_TEST(14, ld, s0, 5)
  45   MISALIGNED_LDST_TEST(15, ld, s0, 6)
  46   MISALIGNED_LDST_TEST(16, ld, s0, 7)
  47 #endif
  48
  49   # indicate it's a store test
  50   li s1, CAUSE_MISALIGNED_STORE
  51
  52   MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
  53   MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
  54   MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
  55   MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
  56
  57 #if __riscv_xlen == 64
  58   MISALIGNED_LDST_TEST(26, sd, s0, 1)
  59   MISALIGNED_LDST_TEST(27, sd, s0, 2)
  60   MISALIGNED_LDST_TEST(28, sd, s0, 3)
  61   MISALIGNED_LDST_TEST(29, sd, s0, 4)
  62   MISALIGNED_LDST_TEST(30, sd, s0, 5)
  63   MISALIGNED_LDST_TEST(31, sd, s0, 6)
  64   MISALIGNED_LDST_TEST(32, sd, s0, 7)
  65 #endif
  66
  67   TEST_PASSFAIL
  68
  69   .align 3
  70 mtvec_handler:
  71   csrr t0, mcause
  72   bne t0, s1, fail
  73
  74   csrr t0, mbadaddr
  75   bne t0, t1, fail
  76
  77   csrr t0, mepc
  78   addi t0, t0, 8
  79   csrw mepc, t0
  80   mret
  81
  82 RVTEST_CODE_END
  83
  84   .data
  85 RVTEST_DATA_BEGIN
  86
  87 data:
  88   .dword 0
  89
  90   TEST_DATA
  91
  92 RVTEST_DATA_END