isa/rv64si/csr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # csr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test CSRRx and CSRRxI instructions.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define sret mret
  22   #define stvec_handler mtvec_handler
  23   #undef SSTATUS_SPP
  24   #define SSTATUS_SPP MSTATUS_MPP
  25 #endif
  26
  27   csrwi sscratch, 3
  28   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
  29   TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
  30   TEST_CASE( 4, a2,         2, csrrsi a2, sscratch, 4);
  31   TEST_CASE( 5, a3,         6, csrrwi a3, sscratch, 2);
  32   TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
  33   TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
  34   TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
  35   TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
  36
  37 #ifdef __MACHINE_MODE
  38   # Is F extension present?
  39   csrr a0, misa
  40   andi a0, a0, (1 << ('F' - 'A'))
  41   beqz a0, 1f
  42   # If so, make sure FP stores have no effect when mstatus.FS is off.
  43   li a1, MSTATUS_FS
  44   csrs mstatus, a1
  45   fmv.s.x f0, x0
  46   csrc mstatus, a1
  47   la a1, fsw_data
  48   TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
  49 1:
  50
  51   # Figure out if 'U' is set in misa
  52   csrr a0, misa   # a0 = csr(misa)
  53   srli a0, a0, 20 # a0 = a0 >> 20
  54   andi a0, a0, 1  # a0 = a0 & 1
  55   beqz a0, finish # if no user mode, skip the rest of these checks
  56 #endif
  57
  58   # jump to user land
  59   li t0, SSTATUS_SPP
  60   csrc sstatus, t0
  61   la t0, 1f
  62   csrw sepc, t0
  63   sret
  64   1:
  65
  66   # Make sure writing the cycle counter causes an exception.
  67   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  68 #ifdef __MACHINE_MODE
  69   TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0);
  70 #endif
  71
  72   # Make sure reading status in user mode causes an exception.
  73   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  74 #ifdef __MACHINE_MODE
  75   TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus)
  76 #else
  77   TEST_CASE(12, x0, 0, nop)
  78 #endif
  79
  80 finish:
  81   RVTEST_PASS
  82
  83   # We should only fall through to this if scall failed.
  84   TEST_PASSFAIL
  85
  86   .align 2
  87 stvec_handler:
  88   # Trapping on tests 10-12 is good news.
  89   # Note that since the test didn't complete, TESTNUM is smaller by 1.
  90   li t0, 9
  91   bltu TESTNUM, t0, 1f
  92   li t0, 11
  93   bleu TESTNUM, t0, privileged
  94 1:
  95
  96   # catch RVTEST_PASS and kick it up to M-mode
  97   csrr t0, scause
  98   li t1, CAUSE_USER_ECALL
  99   bne t0, t1, fail
 100   RVTEST_PASS
 101
 102 privileged:
 103   # Make sure scause indicates a lack of privilege.
 104   csrr t0, scause
 105   li t1, CAUSE_ILLEGAL_INSTRUCTION
 106   bne t0, t1, fail
 107   # Return to user mode, but skip the trapping instruction.
 108   csrr t0, sepc
 109   addi t0, t0, 4
 110   csrw sepc, t0
 111   sret
 112
 113 RVTEST_CODE_END
 114
 115   .data
 116 RVTEST_DATA_BEGIN
 117
 118 fsw_data: .word 1
 119
 120 RVTEST_DATA_END