isa/rv64si/csr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # csr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test CSRRx and CSRRxI instructions.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define sret mret
  22   #define stvec_handler mtvec_handler
  23   #undef SSTATUS_SPP
  24   #define SSTATUS_SPP MSTATUS_MPP
  25 #endif
  26
  27   csrwi sscratch, 3
  28   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
  29   TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
  30   TEST_CASE( 4, a2,         2, csrrsi a2, sscratch, 4);
  31   TEST_CASE( 5, a3,         6, csrrwi a3, sscratch, 2);
  32   TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
  33   TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
  34   TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
  35   TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
  36
  37 #ifdef __MACHINE_MODE
  38   # Figure out if 'U' is set in misa
  39   csrr a0, misa   # a0 = csr(misa)
  40   srli a0, a0, 20 # a0 = a0 >> 20
  41   andi a0, a0, 1  # a0 = a0 & 1
  42   beqz a0, finish # if no user mode, skip the rest of these checks
  43 #endif
  44
  45   # jump to user land
  46   li t0, SSTATUS_SPP
  47   csrc sstatus, t0
  48   la t0, 1f
  49   csrw sepc, t0
  50   sret
  51   1:
  52
  53   # Make sure writing the cycle counter causes an exception.
  54   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  55 #ifdef __MACHINE_MODE
  56   TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
  57 #endif
  58
  59   # Make sure reading status in user mode causes an exception.
  60   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  61 #ifdef __MACHINE_MODE
  62   TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus)
  63 #else
  64   TEST_CASE(11, x0, 0, nop)
  65 #endif
  66
  67 finish:
  68   RVTEST_PASS
  69
  70   # We should only fall through to this if scall failed.
  71   TEST_PASSFAIL
  72
  73   .align 2
  74 stvec_handler:
  75   # Trapping on tests 10 and 11 is good news.
  76   # Note that since the test didn't complete, TESTNUM is smaller by 1.
  77   li t0, 9
  78   beq TESTNUM, t0, privileged
  79   li t0, 10
  80   beq TESTNUM, t0, privileged
  81
  82   # catch RVTEST_PASS and kick it up to M-mode
  83   csrr t0, scause
  84   li t1, CAUSE_USER_ECALL
  85   bne t0, t1, fail
  86   RVTEST_PASS
  87
  88 privileged:
  89   # Make sure scause indicates a lack of privilege.
  90   csrr t0, scause
  91   li t1, CAUSE_ILLEGAL_INSTRUCTION
  92   bne t0, t1, fail
  93   # Return to user mode, but skip the trapping instruction.
  94   csrr t0, sepc
  95   addi t0, t0, 4
  96   csrw sepc, t0
  97   sret
  98
  99 RVTEST_CODE_END
 100
 101   .data
 102 RVTEST_DATA_BEGIN
 103
 104   TEST_DATA
 105
 106 RVTEST_DATA_END