5a8edbeaaf5ff28fcd7acc3701a5bd6d73057811
[riscv-tests.git] / isa / rv64si / csr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # csr.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test CSRRx and CSRRxI instructions.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 #ifdef __MACHINE_MODE
17 #define sscratch mscratch
18 #define sstatus mstatus
19 #define scause mcause
20 #define sepc mepc
21 #define sret mret
22 #define stvec_handler mtvec_handler
23 #undef SSTATUS_SPP
24 #define SSTATUS_SPP MSTATUS_MPP
25 #endif
26
27 # For RV64, make sure UXL encodes RV64. (UXL does not exist for RV32.)
28 #if __riscv_xlen == 64
29 # If running in M mode, read misa to check existence of U mode.
30 # Otherwise, if in S mode, then U mode must exist and we don't need to check.
31 #ifdef __MACHINE_MODE
32 csrr a0, misa
33 srli a0, a0, 'U' - 'A'
34 andi a0, a0, 1
35 beqz a0, 1f
36 #endif
37 # If U mode is present, UXL should be 2 (XLEN = 64-bit)
38 TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
39 #ifdef __MACHINE_MODE
40 j 2f
41 1:
42 # If U mode is not present, UXL should be 0
43 TEST_CASE(14, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
44 2:
45 #endif
46 #endif
47
48 csrwi sscratch, 3
49 TEST_CASE( 2, a0, 3, csrr a0, sscratch);
50 TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1);
51 TEST_CASE( 4, a2, 2, csrrsi a2, sscratch, 4);
52 TEST_CASE( 5, a3, 6, csrrwi a3, sscratch, 2);
53 TEST_CASE( 6, a1, 2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
54 TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
55 TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
56 TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
57
58 #ifdef __MACHINE_MODE
59 # Is F extension present?
60 csrr a0, misa
61 andi a0, a0, (1 << ('F' - 'A'))
62 beqz a0, 1f
63 # If so, make sure FP stores have no effect when mstatus.FS is off.
64 li a1, MSTATUS_FS
65 csrs mstatus, a1
66 #ifdef __riscv_flen
67 fmv.s.x f0, x0
68 csrc mstatus, a1
69 la a1, fsw_data
70 TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
71 #else
72 # Fail if this test is compiled without F but executed on a core with F.
73 TEST_CASE(10, zero, 1)
74 #endif
75 1:
76
77 # Figure out if 'U' is set in misa
78 csrr a0, misa # a0 = csr(misa)
79 srli a0, a0, 20 # a0 = a0 >> 20
80 andi a0, a0, 1 # a0 = a0 & 1
81 beqz a0, finish # if no user mode, skip the rest of these checks
82 #endif /* __MACHINE_MODE */
83
84 # jump to user land
85 li t0, SSTATUS_SPP
86 csrc sstatus, t0
87 la t0, 1f
88 csrw sepc, t0
89 sret
90 1:
91
92 # Make sure writing the cycle counter causes an exception.
93 # Don't run in supervisor, as we don't delegate illegal instruction traps.
94 #ifdef __MACHINE_MODE
95 TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0);
96 #endif
97
98 # Make sure reading status in user mode causes an exception.
99 # Don't run in supervisor, as we don't delegate illegal instruction traps.
100 #ifdef __MACHINE_MODE
101 TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus)
102 #else
103 TEST_CASE(12, x0, 0, nop)
104 #endif
105
106 finish:
107 RVTEST_PASS
108
109 # We should only fall through to this if scall failed.
110 TEST_PASSFAIL
111
112 .align 2
113 .global stvec_handler
114 stvec_handler:
115 # Trapping on tests 10-12 is good news.
116 # Note that since the test didn't complete, TESTNUM is smaller by 1.
117 li t0, 9
118 bltu TESTNUM, t0, 1f
119 li t0, 11
120 bleu TESTNUM, t0, privileged
121 1:
122
123 # catch RVTEST_PASS and kick it up to M-mode
124 csrr t0, scause
125 li t1, CAUSE_USER_ECALL
126 bne t0, t1, fail
127 RVTEST_PASS
128
129 privileged:
130 # Make sure scause indicates a lack of privilege.
131 csrr t0, scause
132 li t1, CAUSE_ILLEGAL_INSTRUCTION
133 bne t0, t1, fail
134 # Return to user mode, but skip the trapping instruction.
135 csrr t0, sepc
136 addi t0, t0, 4
137 csrw sepc, t0
138 sret
139
140 RVTEST_CODE_END
141
142 .data
143 RVTEST_DATA_BEGIN
144
145 fsw_data: .word 1
146
147 RVTEST_DATA_END