isa/rv64si/dirty.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # dirty.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test VM referenced and dirty bits.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Turn on VM
  17   li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
  18   la a1, page_table_1
  19   srl a1, a1, RISCV_PGSHIFT
  20   or a1, a1, a0
  21   csrw sptbr, a1
  22   sfence.vma
  23
  24   # Set up MPRV with MPP=S, so loads and stores use S-mode
  25   li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
  26   csrs mstatus, a1
  27
  28   # Try a faulting store to make sure dirty bit is not set
  29   li TESTNUM, 2
  30   li t2, 1
  31   sw t2, dummy - DRAM_BASE, t1
  32
  33   # Set SUM=1 so user memory access is permitted
  34   li TESTNUM, 3
  35   li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
  36   csrs mstatus, a1
  37
  38   # Make sure SUM=1 works
  39   lw t0, dummy - DRAM_BASE
  40   bnez t0, die
  41
  42   # Try a non-faulting store to make sure dirty bit is set
  43   sw t2, dummy - DRAM_BASE, t1
  44
  45   # Make sure it succeeded
  46   lw t0, dummy - DRAM_BASE
  47   bne t0, t2, die
  48
  49   # Leave MPRV
  50   li t0, MSTATUS_MPRV
  51   csrc mstatus, t0
  52
  53   # Make sure D bit is set
  54   lw t0, page_table_1
  55   li t1, PTE_A | PTE_D
  56   and t0, t0, t1
  57   bne t0, t1, die
  58
  59   RVTEST_PASS
  60
  61   TEST_PASSFAIL
  62
  63   .align 2
  64 mtvec_handler:
  65   csrr t0, mcause
  66   add t0, t0, -CAUSE_STORE_PAGE_FAULT
  67   bnez t0, die
  68
  69   li t1, 2
  70   bne TESTNUM, t1, 1f
  71   # Make sure D bit is clear
  72   lw t0, page_table_1
  73   and t1, t0, PTE_D
  74   bnez t1, die
  75 skip:
  76   csrr t0, mepc
  77   add t0, t0, 4
  78   csrw mepc, t0
  79   mret
  80
  81 1:
  82   li t1, 3
  83   bne TESTNUM, t1, 1f
  84   # The implementation doesn't appear to set D bits in HW.  Skip the test,
  85   # after making sure the D bit is clear.
  86   lw t0, page_table_1
  87   and t1, t0, PTE_D
  88   bnez t1, die
  89   j pass
  90
  91 1:
  92 die:
  93   RVTEST_FAIL
  94
  95 RVTEST_CODE_END
  96
  97   .data
  98 RVTEST_DATA_BEGIN
  99
 100   TEST_DATA
 101
 102 .align 12
 103 page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A
 104 dummy: .dword 0
 105
 106 RVTEST_DATA_END