isa/rv64si/dirty.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # dirty.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test VM referenced and dirty bits.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Turn on VM with superpage identity mapping
  17   li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
  18   la a1, page_table_1
  19   srl a1, a1, RISCV_PGSHIFT
  20   or a1, a1, a0
  21   la a2, page_table_2
  22   srl a2, a2, RISCV_PGSHIFT
  23   or a2, a2, a0
  24   csrw sptbr, a1
  25   sfence.vma
  26   li a1, (MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S
  27   csrs mstatus, a1
  28   la a1, 1f - DRAM_BASE
  29   csrw mepc, a1
  30   la a1, stvec_handler - DRAM_BASE
  31   csrw stvec, a1
  32   mret
  33 1:
  34
  35   # Try a faulting store to make sure dirty bit is not set
  36   li TESTNUM, 2
  37   li t0, 1
  38   sw t0, dummy, t1
  39
  40   # Load new page table
  41   li TESTNUM, 3
  42   csrw sptbr, a2
  43   sfence.vma
  44
  45   # Try a non-faulting store to make sure dirty bit is set
  46   sw t0, dummy, t1
  47
  48   # Make sure D bit is set
  49   lw t0, page_table_2
  50   li t1, PTE_A | PTE_D
  51   and t0, t0, t1
  52   bne t0, t1, die
  53
  54   RVTEST_PASS
  55
  56   TEST_PASSFAIL
  57
  58   .align 2
  59 stvec_handler:
  60   csrr t0, scause
  61   add t0, t0, -CAUSE_FAULT_STORE
  62   bnez t0, die
  63
  64   li t1, 2
  65   bne TESTNUM, t1, 1f
  66   # Make sure D bit is clear
  67   lw t0, page_table_1
  68   and t1, t0, PTE_D
  69   bnez t1, die
  70 skip:
  71   csrr t0, sepc
  72   add t0, t0, 4
  73   csrw sepc, t0
  74   sret
  75
  76 1:
  77   li t1, 3
  78   bne TESTNUM, t1, 1f
  79   # The implementation doesn't appear to set D bits in HW.  Skip the test,
  80   # after making sure the D bit is clear.
  81   lw t0, page_table_2
  82   and t1, t0, PTE_D
  83   bnez t1, die
  84   j pass
  85
  86 1:
  87 die:
  88   RVTEST_FAIL
  89
  90 RVTEST_CODE_END
  91
  92   .data
  93 RVTEST_DATA_BEGIN
  94
  95   TEST_DATA
  96
  97 .align 12
  98 page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_A
  99 dummy: .dword 0
 100 .align 12
 101 page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W | PTE_A
 102
 103 RVTEST_DATA_END