isa/rv64si/dirty.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # dirty.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test VM referenced and dirty bits.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Turn on VM with superpage identity mapping
  17   la a1, handler
  18   csrw stvec, a1
  19   la a1, page_table_1
  20   csrw sptbr, a1
  21   sfence.vm
  22   li a1, (MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV43
  23   csrs mstatus, a1
  24   la a1, 1f
  25   csrw mepc, a1
  26   mret
  27 1:
  28
  29   # Try a faulting store to make sure dirty bit is not set
  30   li TESTNUM, 2
  31   li t0, 1
  32   sd t0, dummy, t1
  33
  34   # Load new page table
  35   li TESTNUM, 3
  36   la t0, page_table_2
  37   csrw sptbr, t0
  38   sfence.vm
  39
  40   # Try a non-faulting store to make sure dirty bit is set
  41   sd t0, dummy, t1
  42
  43   # Make sure R and D bits are set
  44   lw t0, page_table_2
  45   li t1, PTE_R | PTE_D
  46   and t0, t0, t1
  47   bne t0, t1, die
  48
  49   RVTEST_PASS
  50
  51   TEST_PASSFAIL
  52
  53 handler:
  54   csrr t0, scause
  55   li t1, 2
  56   bne TESTNUM, t1, 1f
  57   # Make sure R bit is set
  58   lw t0, page_table_1
  59   li t1, PTE_R
  60   and t0, t0, t1
  61   bne t0, t1, die
  62
  63   # Make sure D bit is clear
  64   lw t0, page_table_1
  65   li t1, PTE_D
  66   and t0, t0, t1
  67   beq t0, t1, die
  68
  69   csrr t0, sepc
  70   add t0, t0, 4
  71   csrw sepc, t0
  72   sret
  73
  74 die:
  75   RVTEST_FAIL
  76
  77 .data
  78 .align 13
  79 page_table_1: .dword PTE_V | PTE_SX | PTE_SR
  80 dummy: .dword 0
  81 .align 13
  82 page_table_2: .dword PTE_V | PTE_SX | PTE_SR | PTE_SW
  83
  84 RVTEST_CODE_END