4845338b92a0acd458e8f789013055f0975d960c
[riscv-tests.git] / isa / rv64si / ipi.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ipi.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test interprocessor interrupts.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 # clear pending IPIs then enable interrupts
17 la a0, handler
18 csrw evec, a0
19 csrw clear_ipi, x0
20 li a0, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
21 csrs status, a0
22
23 # wait for all cores to boot
24 la a0, coreid
25 li a1, 1
26 amoadd.w x0, a1, 0(a0)
27 lw a3, 4(x0)
28 1: lw a1, 0(a0)
29 blt a1, a3, 1b
30
31 # IPI dominoes
32 csrr a0, hartid
33 1: bnez a0, 1b
34 add a0, a0, 1
35 rem a0, a0, a3
36 csrw send_ipi, a0
37 1: j 1b
38
39 handler:
40 csrr a0, hartid
41 bnez a0, 2f
42 RVTEST_PASS
43
44 TEST_PASSFAIL
45
46 2: add a0, a0, 1
47 rem a0, a0, a3
48 csrw send_ipi, a0
49 1: j 1b
50
51 RVTEST_CODE_END
52
53 .data
54 RVTEST_DATA_BEGIN
55
56 TEST_DATA
57
58 coreid: .word 0
59 foo: .word 0
60
61 RVTEST_DATA_END