e45c66321f424bdeebae728930c2252b584ae028
[riscv-tests.git] / isa / rv64si / ipi.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ipi.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test interprocessor interrupts.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64M
14 RVTEST_CODE_BEGIN
15
16 # enable interrupts
17 csrs mstatus, MSTATUS_IE
18
19 # get a unique core id
20 la a0, coreid
21 li a1, 1
22 amoadd.w a2, a1, (a0)
23
24 # for now, only run this on core 0
25 1:li a3, 1
26 bgeu a2, a3, 1b
27
28 # wait for all cores to boot
29 1: lw a1, (a0)
30 bltu a1, a3, 1b
31
32 # IPI dominoes
33 csrr a0, hartid
34 1: bnez a0, 1b
35 add a0, a0, 1
36 rem a0, a0, a3
37 csrw send_ipi, a0
38 1: j 1b
39
40 mtvec:
41 csrr a0, hartid
42 bnez a0, 2f
43 RVTEST_PASS
44
45 TEST_PASSFAIL
46
47 2: add a0, a0, 1
48 rem a0, a0, a3
49 csrw send_ipi, a0
50 1: j 1b
51
52 RVTEST_CODE_END
53
54 .data
55 RVTEST_DATA_BEGIN
56
57 TEST_DATA
58
59 coreid: .word 0
60 foo: .word 0
61
62 RVTEST_DATA_END