isa/rv64si/ma_addr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_addr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ld/st trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16   la s0, stvec_load
  17
  18   la t0, stvec_load
  19   csrw stvec, t0
  20
  21 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
  22   li TESTNUM, testnum; \
  23   insn x0, offset(base); \
  24   j fail \
  25
  26   MISALIGNED_LDST_TEST(2,  lh,  s0, 1)
  27   MISALIGNED_LDST_TEST(3,  lhu, s0, 1)
  28   MISALIGNED_LDST_TEST(4,  lw,  s0, 1)
  29   MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
  30   MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
  31
  32 #ifdef __riscv64
  33   MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
  34   MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
  35   MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
  36
  37   MISALIGNED_LDST_TEST(10, ld, s0, 1)
  38   MISALIGNED_LDST_TEST(11, ld, s0, 2)
  39   MISALIGNED_LDST_TEST(12, ld, s0, 3)
  40   MISALIGNED_LDST_TEST(13, ld, s0, 4)
  41   MISALIGNED_LDST_TEST(14, ld, s0, 5)
  42   MISALIGNED_LDST_TEST(15, ld, s0, 6)
  43   MISALIGNED_LDST_TEST(16, ld, s0, 7)
  44 #endif
  45
  46   la t0, stvec_store
  47   csrw stvec, t0
  48
  49   MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
  50   MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
  51   MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
  52   MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
  53
  54 #ifdef __riscv64
  55   MISALIGNED_LDST_TEST(26, sd, s0, 1)
  56   MISALIGNED_LDST_TEST(27, sd, s0, 2)
  57   MISALIGNED_LDST_TEST(28, sd, s0, 3)
  58   MISALIGNED_LDST_TEST(29, sd, s0, 4)
  59   MISALIGNED_LDST_TEST(30, sd, s0, 5)
  60   MISALIGNED_LDST_TEST(31, sd, s0, 6)
  61   MISALIGNED_LDST_TEST(32, sd, s0, 7)
  62 #endif
  63
  64   TEST_PASSFAIL
  65
  66   .align 3
  67 stvec_load:
  68   li t1, CAUSE_MISALIGNED_LOAD
  69   csrr t0, scause
  70   bne t0, t1, fail
  71   csrr t0, sepc
  72   addi t0, t0, 8
  73   csrw sepc, t0
  74   sret
  75
  76 stvec_store:
  77   li t1, CAUSE_MISALIGNED_STORE
  78   csrr t0, scause
  79   bne t0, t1, fail
  80   csrr t0, sepc
  81   addi t0, t0, 8
  82   csrw sepc, t0
  83   sret
  84
  85 RVTEST_CODE_END
  86
  87   .data
  88 RVTEST_DATA_BEGIN
  89
  90   TEST_DATA
  91
  92 RVTEST_DATA_END