isa/rv64si/ma_addr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_addr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ld/st trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define stvec_handler mtvec_handler
  22 #endif
  23
  24   la s0, stvec_handler
  25
  26   # indicate it's a load test
  27   li s1, 0
  28
  29 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
  30   li TESTNUM, testnum; \
  31   insn x0, offset(base); \
  32   j fail \
  33
  34   MISALIGNED_LDST_TEST(2,  lh,  s0, 1)
  35   MISALIGNED_LDST_TEST(3,  lhu, s0, 1)
  36   MISALIGNED_LDST_TEST(4,  lw,  s0, 1)
  37   MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
  38   MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
  39
  40 #ifdef __riscv64
  41   MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
  42   MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
  43   MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
  44
  45   MISALIGNED_LDST_TEST(10, ld, s0, 1)
  46   MISALIGNED_LDST_TEST(11, ld, s0, 2)
  47   MISALIGNED_LDST_TEST(12, ld, s0, 3)
  48   MISALIGNED_LDST_TEST(13, ld, s0, 4)
  49   MISALIGNED_LDST_TEST(14, ld, s0, 5)
  50   MISALIGNED_LDST_TEST(15, ld, s0, 6)
  51   MISALIGNED_LDST_TEST(16, ld, s0, 7)
  52 #endif
  53
  54   # indicate it's a store test
  55   li s1, 1
  56
  57   MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
  58   MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
  59   MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
  60   MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
  61
  62 #ifdef __riscv64
  63   MISALIGNED_LDST_TEST(26, sd, s0, 1)
  64   MISALIGNED_LDST_TEST(27, sd, s0, 2)
  65   MISALIGNED_LDST_TEST(28, sd, s0, 3)
  66   MISALIGNED_LDST_TEST(29, sd, s0, 4)
  67   MISALIGNED_LDST_TEST(30, sd, s0, 5)
  68   MISALIGNED_LDST_TEST(31, sd, s0, 6)
  69   MISALIGNED_LDST_TEST(32, sd, s0, 7)
  70 #endif
  71
  72   TEST_PASSFAIL
  73
  74   .align 3
  75 stvec_handler:
  76   bnez s1, test_store
  77
  78 test_load:
  79   li t1, CAUSE_MISALIGNED_LOAD
  80   csrr t0, scause
  81   bne t0, t1, fail
  82   csrr t0, sepc
  83   addi t0, t0, 8
  84   csrw sepc, t0
  85   sret
  86
  87 test_store:
  88   li t1, CAUSE_MISALIGNED_STORE
  89   csrr t0, scause
  90   bne t0, t1, fail
  91   csrr t0, sepc
  92   addi t0, t0, 8
  93   csrw sepc, t0
  94   sret
  95
  96 RVTEST_CODE_END
  97
  98   .data
  99 RVTEST_DATA_BEGIN
 100
 101   TEST_DATA
 102
 103 RVTEST_DATA_END