isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define sret mret
  22   #define stvec_handler mtvec_handler
  23 #endif
  24
  25   .option norvc
  26
  27   # Without RVC, the jalr should trap, and the handler will skip ahead.
  28   # With RVC, the jalr should not trap, and "j fail" should get skipped.
  29   li TESTNUM, 2
  30   li t1, 0
  31   la t0, 1f
  32   jalr t1, t0, 2
  33 1:
  34   .option rvc
  35   c.j 1f
  36   c.j 2f
  37   .option norvc
  38 1:
  39   j fail
  40 2:
  41
  42   // This test should pass, since JALR ignores the target LSB
  43   li TESTNUM, 3
  44   la t0, 1f
  45   jalr t1, t0, 1
  46 1:
  47   j 1f
  48   j fail
  49 1:
  50
  51   li TESTNUM, 4
  52   li t1, 0
  53   la t0, 1f
  54   jalr t1, t0, 3
  55 1:
  56   .option rvc
  57   c.j 1f
  58   c.j 2f
  59   .option norvc
  60 1:
  61   j fail
  62 2:
  63
  64   j pass
  65
  66   TEST_PASSFAIL
  67
  68   .align 2
  69 stvec_handler:
  70   # tests 2 and 4 should trap
  71   li a0, 2
  72   beq TESTNUM, a0, 1f
  73   li a0, 4
  74   beq TESTNUM, a0, 1f
  75   j fail
  76 1:
  77
  78   # verify that return address was not written
  79   bnez t1, fail
  80
  81   # verify trap cause
  82   li a1, CAUSE_MISALIGNED_FETCH
  83   csrr a0, scause
  84   bne a0, a1, fail
  85
  86   # verify that epc == &jalr (== t0 - 4)
  87   csrr a1, sepc
  88   addi t0, t0, -4
  89   bne t0, a1, fail
  90
  91   addi a1, a1, 12
  92   csrw sepc, a1
  93   sret
  94
  95 RVTEST_CODE_END
  96
  97   .data
  98 RVTEST_DATA_BEGIN
  99
 100   TEST_DATA
 101
 102 RVTEST_DATA_END