isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16   la t0, stvec
  17   csrw stvec, t0
  18
  19 #ifndef __rvc
  20   li TESTNUM, 2
  21   li t1, 0
  22   la t0, 1f
  23   jalr t1, t0, 2
  24 1:
  25   j fail
  26 #endif
  27
  28   // This test should pass, since JALR ignores the target LSB
  29   li TESTNUM, 3
  30   la t0, 1f
  31   jalr t1, t0, 1
  32 1:
  33   j 1f
  34   j fail
  35 1:
  36
  37 #ifndef __rvc
  38   li TESTNUM, 4
  39   li t1, 0
  40   la t0, 3f
  41   jr t0, 3
  42 3:
  43   j fail
  44 #endif
  45
  46   j pass
  47
  48   TEST_PASSFAIL
  49
  50 stvec:
  51   # tests 2 and 4 should trap
  52   li a0, 2
  53   beq TESTNUM, a0, 1f
  54   li a0, 4
  55   beq TESTNUM, a0, 1f
  56   j fail
  57 1:
  58
  59   # verify that return address was not written
  60   bnez t1, fail
  61
  62   # verify trap cause
  63   li a1, CAUSE_MISALIGNED_FETCH
  64   csrr a0, scause
  65   bne a0, a1, fail
  66
  67   # verify that epc == &jalr (== t0 - 4)
  68   csrr a1, sepc
  69   addi t0, t0, -4
  70   bne t0, a1, fail
  71
  72   addi a1, a1, 8
  73   csrw sepc, a1
  74   sret
  75
  76 RVTEST_CODE_END
  77
  78   .data
  79 RVTEST_DATA_BEGIN
  80
  81   TEST_DATA
  82
  83 RVTEST_DATA_END