isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define stvec_handler mtvec_handler
  22 #endif
  23
  24   .option norvc
  25
  26   # Without RVC, the jalr should trap, and the handler will skip ahead.
  27   # With RVC, the jalr should not trap, and "j fail" should get skipped.
  28   li TESTNUM, 2
  29   li t1, 0
  30   la t0, 1f
  31   jalr t1, t0, 2
  32 1:
  33   .option rvc
  34   c.j fail
  35   c.j 2f
  36   .option norvc
  37   j fail
  38 2:
  39
  40   // This test should pass, since JALR ignores the target LSB
  41   li TESTNUM, 3
  42   la t0, 1f
  43   jalr t1, t0, 1
  44 1:
  45   j 1f
  46   j fail
  47 1:
  48
  49   li TESTNUM, 4
  50   li t1, 0
  51   la t0, 1f
  52   jalr t1, t0, 3
  53 1:
  54   .option rvc
  55   c.j fail
  56   c.j 2f
  57   .option norvc
  58   j fail
  59 2:
  60
  61   j pass
  62
  63   TEST_PASSFAIL
  64
  65 stvec_handler:
  66   # tests 2 and 4 should trap
  67   li a0, 2
  68   beq TESTNUM, a0, 1f
  69   li a0, 4
  70   beq TESTNUM, a0, 1f
  71   j fail
  72 1:
  73
  74   # verify that return address was not written
  75   bnez t1, fail
  76
  77   # verify trap cause
  78   li a1, CAUSE_MISALIGNED_FETCH
  79   csrr a0, scause
  80   bne a0, a1, fail
  81
  82   # verify that epc == &jalr (== t0 - 4)
  83   csrr a1, sepc
  84   addi t0, t0, -4
  85   bne t0, a1, fail
  86
  87   addi a1, a1, 12
  88   csrw sepc, a1
  89   sret
  90
  91 RVTEST_CODE_END
  92
  93   .data
  94 RVTEST_DATA_BEGIN
  95
  96   TEST_DATA
  97
  98 RVTEST_DATA_END