isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sbadaddr mbadaddr
  21   #define sepc mepc
  22   #define sret mret
  23   #define stvec_handler mtvec_handler
  24 #endif
  25
  26   .align 2
  27   .option norvc
  28
  29   # Without RVC, the jalr should trap, and the handler will skip ahead.
  30   # With RVC, the jalr should not trap, and "j fail" should get skipped.
  31   li TESTNUM, 2
  32   li t1, 0
  33   la t0, 1f
  34   jalr t1, t0, 2
  35 1:
  36   .option rvc
  37   c.j 1f
  38   c.j 2f
  39   .option norvc
  40 1:
  41   j fail
  42 2:
  43
  44   // This test should pass, since JALR ignores the target LSB
  45   li TESTNUM, 3
  46   la t0, 1f
  47   jalr t1, t0, 1
  48 1:
  49   j 1f
  50   j fail
  51 1:
  52
  53   li TESTNUM, 4
  54   li t1, 0
  55   la t0, 1f
  56   jalr t1, t0, 3
  57 1:
  58   .option rvc
  59   c.j 1f
  60   c.j 2f
  61   .option norvc
  62 1:
  63   j fail
  64 2:
  65
  66   # Like test 2, but with jal instead of jalr.
  67   li TESTNUM, 5
  68   li t1, 0
  69   la t0, 1f
  70   jal t1, 2f
  71 1:
  72   .option rvc
  73   c.j 1f
  74 2:
  75   c.j 2f
  76   .option norvc
  77 1:
  78   j fail
  79 2:
  80
  81   # Like test 2, but with a taken branch instead of jalr.
  82   li TESTNUM, 6
  83   li t1, 0
  84   la t0, 1f
  85   beqz x0, 2f
  86 1:
  87   .option rvc
  88   c.j 1f
  89 2:
  90   c.j 2f
  91   .option norvc
  92 1:
  93   j fail
  94 2:
  95
  96   # Not-taken branches should not trap, even without RVC.
  97   li TESTNUM, 7
  98   bnez x0, 1f
  99   j 2f
 100   .option rvc
 101   c.j 1f
 102 1:
 103   c.j 1f
 104   .option norvc
 105 1:
 106   j fail
 107 2:
 108
 109 #ifdef __MACHINE_MODE
 110   # RVC cannot be disabled if doing so would cause a misaligned instruction
 111   # exception on the next instruction fetch. (This test assumes no other
 112   # extensions that support misalignment are present.)
 113   li TESTNUM, 8
 114   csrr t2, misa
 115   andi t2, t2, 1 << ('c' - 'a')
 116   beqz t2, 2f
 117
 118   .option rvc
 119   c.nop
 120   csrci misa, 1 << ('c' - 'a')
 121 1:
 122   c.nop
 123   .option norvc
 124
 125   csrr t2, misa
 126   andi t2, t2, 1 << ('c' - 'a')
 127   beqz t2, fail
 128
 129   # When RVC is disabled, mret to a misaligned mepc should succeed,
 130   # masking off mepc[1].
 131   la t0, 1f
 132   addi t0, t0, -2
 133   csrw mepc, t0
 134
 135   # Try to disable RVC; if it can't be disabled, skip the test.
 136   csrci misa, 1 << ('c' - 'a')
 137   csrr t2, misa
 138   andi t2, t2, 1 << ('c' - 'a')
 139   bnez t2, 2f
 140
 141   li t2, MSTATUS_MPP
 142   csrs mstatus, t2
 143   mret
 144
 145   # mret should transfer control to this branch.  Otherwise, it will
 146   # transfer control two bytes into the branch, which happens to be the
 147   # illegal instruction c.unimp.
 148   beqz x0, 1f
 149 1:
 150   csrsi misa, 1 << ('c' - 'a')
 151 2:
 152 #endif
 153
 154   j pass
 155
 156   TEST_PASSFAIL
 157
 158   .align 2
 159   .global stvec_handler
 160 stvec_handler:
 161   # tests 2, 4, 5, 6, and 8 should trap
 162   li a0, 2
 163   beq TESTNUM, a0, 1f
 164   li a0, 4
 165   beq TESTNUM, a0, 1f
 166   li a0, 5
 167   beq TESTNUM, a0, 1f
 168   li a0, 6
 169   beq TESTNUM, a0, 1f
 170   j fail
 171 1:
 172
 173   # verify that return address was not written
 174   bnez t1, fail
 175
 176   # verify trap cause
 177   li a1, CAUSE_MISALIGNED_FETCH
 178   csrr a0, scause
 179   bne a0, a1, fail
 180
 181   # verify that epc == &jalr (== t0 - 4)
 182   csrr a1, sepc
 183   addi a1, a1, 4
 184   bne t0, a1, fail
 185
 186   # verify that badaddr == 0 or badaddr == t0+2.
 187   csrr a0, sbadaddr
 188   beqz a0, 1f
 189   addi a0, a0, -2
 190   bne a0, t0, fail
 191 1:
 192
 193   addi a1, a1, 12
 194   csrw sepc, a1
 195   sret
 196
 197 RVTEST_CODE_END
 198
 199   .data
 200 RVTEST_DATA_BEGIN
 201
 202   TEST_DATA
 203
 204 RVTEST_DATA_END