ERET -> xRET; new memory map
[riscv-tests.git] / isa / rv64si / sbreak.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # scall.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test syscall trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 #ifdef __MACHINE_MODE
17 #define sscratch mscratch
18 #define sstatus mstatus
19 #define scause mcause
20 #define sepc mepc
21 #define sret mret
22 #define stvec_handler mtvec_handler
23 #endif
24
25 li TESTNUM, 2
26 sbreak
27 j fail
28
29 j pass
30
31 TEST_PASSFAIL
32
33 stvec_handler:
34 li t1, CAUSE_BREAKPOINT
35 csrr t0, scause
36 bne t0, t1, fail
37 csrr t0, sepc
38 addi t0, t0, 8
39 csrw sepc, t0
40 sret
41
42 RVTEST_CODE_END
43
44 .data
45 RVTEST_DATA_BEGIN
46
47 TEST_DATA
48
49 RVTEST_DATA_END