Revert "Fix to solve the failing tests shamt, csr and scall (#151)"
[riscv-tests.git] / isa / rv64si / scall.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # scall.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test syscall trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 #ifdef __MACHINE_MODE
17 #define sscratch mscratch
18 #define sstatus mstatus
19 #define scause mcause
20 #define sepc mepc
21 #define sret mret
22 #define stvec_handler mtvec_handler
23 #undef SSTATUS_SPP
24 #define SSTATUS_SPP MSTATUS_MPP
25 #endif
26
27 li TESTNUM, 2
28
29 # This is the expected trap code.
30 li t1, CAUSE_USER_ECALL
31
32 #ifdef __MACHINE_MODE
33 # If running in M mode, use mstatus.MPP to check existence of U mode.
34 # Otherwise, if in S mode, then U mode must exist and we don't need to check.
35 li t0, MSTATUS_MPP
36 csrc mstatus, t0
37 csrr t1, mstatus
38 and t0, t0, t1
39 beqz t0, 1f
40
41 # If U mode doesn't exist, mcause should indicate ECALL from M mode.
42 li t1, CAUSE_MACHINE_ECALL
43 #endif
44
45 1:
46 li t0, SSTATUS_SPP
47 csrc sstatus, t0
48 la t0, 1f
49 csrw sepc, t0
50 sret
51 1:
52
53 li TESTNUM, 1
54 do_scall:
55 scall
56 j fail
57
58 TEST_PASSFAIL
59
60 .align 2
61 .global stvec_handler
62 stvec_handler:
63 csrr t0, scause
64 bne t0, t1, fail
65 la t2, do_scall
66 csrr t0, sepc
67 bne t0, t2, fail
68 j pass
69
70 RVTEST_CODE_END
71
72 .data
73 RVTEST_DATA_BEGIN
74
75 TEST_DATA
76
77 RVTEST_DATA_END