Test mstatus.TW, mstatus.TVM, and mstatus.TSR features
[riscv-tests.git] / isa / rv64si / scall.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # scall.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test syscall trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 #ifdef __MACHINE_MODE
17 #define sscratch mscratch
18 #define sstatus mstatus
19 #define scause mcause
20 #define sepc mepc
21 #define sret mret
22 #define stvec_handler mtvec_handler
23 #undef SSTATUS_SPP
24 #define SSTATUS_SPP MSTATUS_MPP
25 #endif
26
27 li TESTNUM, 2
28
29 li t0, SSTATUS_SPP
30 csrc sstatus, t0
31 la t0, 1f
32 csrw sepc, t0
33 sret
34 1:
35
36 li TESTNUM, 1
37 scall
38 j fail
39
40 TEST_PASSFAIL
41
42 .align 2
43 stvec_handler:
44 li t1, CAUSE_USER_ECALL
45 csrr t0, scause
46 bne t0, t1, fail
47 j pass
48
49 RVTEST_CODE_END
50
51 .data
52 RVTEST_DATA_BEGIN
53
54 TEST_DATA
55
56 RVTEST_DATA_END