935b2dd542c2b5c4525944b48ba05907118cdb9b
[riscv-tests.git] / isa / rv64si / scall.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # scall.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test syscall trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 #ifdef __MACHINE_MODE
17 #define sscratch mscratch
18 #define sstatus mstatus
19 #define scause mcause
20 #define sepc mepc
21 #define stvec_handler mtvec_handler
22 #undef CAUSE_SUPERVISOR_ECALL
23 #define CAUSE_SUPERVISOR_ECALL CAUSE_MACHINE_ECALL
24 #endif
25
26 li TESTNUM, 2
27 scall
28 j fail
29
30 j pass
31
32 TEST_PASSFAIL
33
34 stvec_handler:
35 li t1, CAUSE_SUPERVISOR_ECALL
36 csrr t0, scause
37 bne t0, t1, fail
38 csrr t0, sepc
39 addi t0, t0, 8
40 csrw sepc, t0
41 sret
42
43 RVTEST_CODE_END
44
45 .data
46 RVTEST_DATA_BEGIN
47
48 TEST_DATA
49
50 RVTEST_DATA_END