isa/rv64si/timer.S

   1 #*****************************************************************************
   2 # ipi.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test interprocessor interrupts.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64S
  12 RVTEST_CODE_BEGIN
  13
  14   # clear pending IPIs then enable interrupts
  15   li s9, 0
  16   la a0, handler
  17   csrw evec, a0
  18   csrw count, x0
  19   li a1, 5000
  20   csrw compare, a1
  21   li a0, SR_EI | (1 << (IRQ_TIMER + SR_IM_SHIFT))
  22   csrs status, a0
  23
  24   # advance an LFSR 1000 times
  25   li s0, 1023
  26   li s1, 1023
  27   li s4, 0
  28 1:srl s2,s0,3
  29   xor s2,s2,s0
  30   and s2,s2,1
  31   srl s0,s0,1
  32   sll s2,s2,9
  33   or  s0,s2,s0
  34   sll s0,s0,54
  35   srl s0,s0,54
  36   add s4, s4, 1
  37   bne s0,s1,1b
  38
  39   csrc status, SR_EI
  40
  41   li TESTNUM, 2
  42   beqz s9, fail    # make sure we took at least one interrupt
  43   li TESTNUM, 3
  44   bne s4, s1, fail # make sure the LFSR period was correct
  45
  46   RVTEST_PASS
  47
  48   TEST_PASSFAIL
  49
  50 handler:
  51   csrr t0, cause
  52   li t1, 0x8000000000000007
  53   bne t0, t1, fail
  54
  55   csrr t0, compare
  56   addi t0, t0, 99
  57   csrw compare, t0
  58
  59   add s9, s9, 1
  60
  61   sret
  62
  63 RVTEST_CODE_END