revamp vector tests with new privileged spec, and add scalar pt tests
[riscv-tests.git] / isa / rv64sv / illegal_cfg_nfpr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal_tvec_cmd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal tvec command trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 la a3,handler
17 csrw stvec,a3 # set exception handler
18
19 li a0,33
20 slli a0,a0,6
21 vsetcfg a0
22
23 vtcode2:
24 add x2,x2,x3
25 stop
26
27 handler:
28 vxcptkill
29
30 li TESTNUM,2
31
32 # check cause
33 vxcptcause a3
34 li a4,HWACHA_CAUSE_ILLEGAL_CFG
35 bne a3,a4,fail
36
37 # check vec irq aux
38 vxcptaux a3
39 li a4, 1
40 bne a3,a4,fail
41
42 # make sure vector unit has cleared out
43 vsetcfg 32,0
44 li a3,4
45 vsetvl a3,a3
46
47 la a3,src1
48 la a4,src2
49 vld vx2,a3
50 vld vx3,a4
51 lui a0,%hi(vtcode2)
52 vf %lo(vtcode2)(a0)
53 la a5,dest
54 vsd vx2,a5
55 fence
56
57 ld a1,0(a5)
58 li a2,5
59 li TESTNUM,2
60 bne a1,a2,fail
61 ld a1,8(a5)
62 li TESTNUM,3
63 bne a1,a2,fail
64 ld a1,16(a5)
65 li TESTNUM,4
66 bne a1,a2,fail
67 ld a1,24(a5)
68 li TESTNUM,5
69 bne a1,a2,fail
70
71 TEST_PASSFAIL
72
73 RVTEST_CODE_END
74
75 .data
76 RVTEST_DATA_BEGIN
77
78 TEST_DATA
79
80 src1:
81 .dword 1
82 .dword 2
83 .dword 3
84 .dword 4
85 src2:
86 .dword 4
87 .dword 3
88 .dword 2
89 .dword 1
90 dest:
91 .dword 0xdeadbeefcafebabe
92 .dword 0xdeadbeefcafebabe
93 .dword 0xdeadbeefcafebabe
94 .dword 0xdeadbeefcafebabe
95
96 RVTEST_DATA_END