isa/rv64sv/illegal_cfg_nfpr.S

   1 #*****************************************************************************
   2 # illegal_tvec_cmd.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test illegal tvec command trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64S
  12 RVTEST_CODE_BEGIN
  13
  14   li a0, SR_EA | SR_EI
  15   csrs status, a0
  16
  17   la a3,handler
  18   csrw evec,a3 # set exception handler
  19
  20   csrr a3,status
  21   li a4,(1 << IRQ_COP)
  22   slli a4,a4,SR_IM_SHIFT
  23   or a3,a3,a4 # enable IM[COP]
  24   csrw status,a3
  25
  26   li a0,33
  27   slli a0,a0,6
  28   vsetcfg a0
  29
  30 vtcode2:
  31   add x2,x2,x3
  32   stop
  33
  34 handler:
  35   vxcptkill
  36
  37   li TESTNUM,2
  38
  39   # check cause
  40   vxcptcause a3
  41   li a4,HWACHA_CAUSE_ILLEGAL_CFG
  42   bne a3,a4,fail
  43
  44   # check vec irq aux
  45   vxcptaux a3
  46   li a4, 1
  47   bne a3,a4,fail
  48
  49   # make sure vector unit has cleared out
  50   vsetcfg 32,0
  51   li a3,4
  52   vsetvl a3,a3
  53
  54   la a3,src1
  55   la a4,src2
  56   vld vx2,a3
  57   vld vx3,a4
  58   lui a0,%hi(vtcode2)
  59   vf %lo(vtcode2)(a0)
  60   la a5,dest
  61   vsd vx2,a5
  62   fence
  63
  64   ld a1,0(a5)
  65   li a2,5
  66   li TESTNUM,2
  67   bne a1,a2,fail
  68   ld a1,8(a5)
  69   li TESTNUM,3
  70   bne a1,a2,fail
  71   ld a1,16(a5)
  72   li TESTNUM,4
  73   bne a1,a2,fail
  74   ld a1,24(a5)
  75   li TESTNUM,5
  76   bne a1,a2,fail
  77
  78   TEST_PASSFAIL
  79
  80 RVTEST_CODE_END
  81
  82   .data
  83 RVTEST_DATA_BEGIN
  84
  85   TEST_DATA
  86
  87 src1:
  88   .dword 1
  89   .dword 2
  90   .dword 3
  91   .dword 4
  92 src2:
  93   .dword 4
  94   .dword 3
  95   .dword 2
  96   .dword 1
  97 dest:
  98   .dword 0xdeadbeefcafebabe
  99   .dword 0xdeadbeefcafebabe
 100   .dword 0xdeadbeefcafebabe
 101   .dword 0xdeadbeefcafebabe
 102
 103 RVTEST_DATA_END