split out S-mode tests and M-mode tests
[riscv-tests.git] / isa / rv64sv / illegal_cfg_nxpr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal_tvec_cmd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal tvec command trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 li a0,33
17 vsetcfg a0
18
19 vtcode2:
20 add x2,x2,x3
21 stop
22
23 stvec_handler:
24 vxcptkill
25
26 li TESTNUM,2
27
28 # check cause
29 csrr a3, scause
30 li a4,HWACHA_CAUSE_ILLEGAL_CFG
31 bne a3,a4,fail
32
33 # check vec irq aux
34 csrr a3, sbadaddr
35 li a4, 0
36 bne a3,a4,fail
37
38 # make sure vector unit has cleared out
39 vsetcfg 32,0
40 li a3,4
41 vsetvl a3,a3
42
43 la a3,src1
44 la a4,src2
45 vld vx2,a3
46 vld vx3,a4
47 lui a0,%hi(vtcode2)
48 vf %lo(vtcode2)(a0)
49 la a5,dest
50 vsd vx2,a5
51 fence
52
53 ld a1,0(a5)
54 li a2,5
55 li TESTNUM,2
56 bne a1,a2,fail
57 ld a1,8(a5)
58 li TESTNUM,3
59 bne a1,a2,fail
60 ld a1,16(a5)
61 li TESTNUM,4
62 bne a1,a2,fail
63 ld a1,24(a5)
64 li TESTNUM,5
65 bne a1,a2,fail
66
67 TEST_PASSFAIL
68
69 RVTEST_CODE_END
70
71 .data
72 RVTEST_DATA_BEGIN
73
74 TEST_DATA
75
76 src1:
77 .dword 1
78 .dword 2
79 .dword 3
80 .dword 4
81 src2:
82 .dword 4
83 .dword 3
84 .dword 2
85 .dword 1
86 dest:
87 .dword 0xdeadbeefcafebabe
88 .dword 0xdeadbeefcafebabe
89 .dword 0xdeadbeefcafebabe
90 .dword 0xdeadbeefcafebabe
91
92 RVTEST_DATA_END