revamp vector tests with new privileged spec, and add scalar pt tests
[riscv-tests.git] / isa / rv64sv / illegal_cfg_nxpr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal_tvec_cmd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal tvec command trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 la a3,handler
17 csrw stvec,a3 # set exception handler
18
19 li a0,33
20 vsetcfg a0
21
22 vtcode2:
23 add x2,x2,x3
24 stop
25
26 handler:
27 vxcptkill
28
29 li TESTNUM,2
30
31 # check cause
32 vxcptcause a3
33 li a4,HWACHA_CAUSE_ILLEGAL_CFG
34 bne a3,a4,fail
35
36 # check vec irq aux
37 vxcptaux a3
38 li a4, 0
39 bne a3,a4,fail
40
41 # make sure vector unit has cleared out
42 vsetcfg 32,0
43 li a3,4
44 vsetvl a3,a3
45
46 la a3,src1
47 la a4,src2
48 vld vx2,a3
49 vld vx3,a4
50 lui a0,%hi(vtcode2)
51 vf %lo(vtcode2)(a0)
52 la a5,dest
53 vsd vx2,a5
54 fence
55
56 ld a1,0(a5)
57 li a2,5
58 li TESTNUM,2
59 bne a1,a2,fail
60 ld a1,8(a5)
61 li TESTNUM,3
62 bne a1,a2,fail
63 ld a1,16(a5)
64 li TESTNUM,4
65 bne a1,a2,fail
66 ld a1,24(a5)
67 li TESTNUM,5
68 bne a1,a2,fail
69
70 TEST_PASSFAIL
71
72 RVTEST_CODE_END
73
74 .data
75 RVTEST_DATA_BEGIN
76
77 TEST_DATA
78
79 src1:
80 .dword 1
81 .dword 2
82 .dword 3
83 .dword 4
84 src2:
85 .dword 4
86 .dword 3
87 .dword 2
88 .dword 1
89 dest:
90 .dword 0xdeadbeefcafebabe
91 .dword 0xdeadbeefcafebabe
92 .dword 0xdeadbeefcafebabe
93 .dword 0xdeadbeefcafebabe
94
95 RVTEST_DATA_END