Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git] / isa / rv64sv / illegal_inst.S
1 #*****************************************************************************
2 # illegal_tvec_cmd.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal tvec command trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 li a0, SR_EA | SR_EI
15 csrs status, a0
16
17 la a3,handler
18 csrw evec,a3 # set exception handler
19
20 csrr a3,status
21 li a4,(1 << IRQ_COP)
22 slli a4,a4,SR_IM_SHIFT
23 or a3,a3,a4 # enable IM[COP]
24 csrw status,a3
25
26 .word 0xff00002b
27
28 vsetcfg 32,0
29 li a3,4
30 vsetvl a3,a3
31
32 vtcode1:
33 lw x2, 0(x1)
34 stop
35
36 vtcode2:
37 add x2,x2,x3
38 stop
39
40 handler:
41 vxcptkill
42
43 li TESTNUM,2
44
45 # check cause
46 vxcptcause a3
47 li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION
48 bne a3,a4,fail
49
50 # check vec irq aux
51 vxcptaux a3
52 li a4, 0xff00002b
53 bne a3,a4,fail
54
55 # make sure vector unit has cleared out
56 vsetcfg 32,0
57 li a3,4
58 vsetvl a3,a3
59
60 la a3,src1
61 la a4,src2
62 vld vx2,a3
63 vld vx3,a4
64 lui a0,%hi(vtcode2)
65 vf %lo(vtcode2)(a0)
66 la a5,dest
67 vsd vx2,a5
68 fence
69
70 ld a1,0(a5)
71 li a2,5
72 li TESTNUM,2
73 bne a1,a2,fail
74 ld a1,8(a5)
75 li TESTNUM,3
76 bne a1,a2,fail
77 ld a1,16(a5)
78 li TESTNUM,4
79 bne a1,a2,fail
80 ld a1,24(a5)
81 li TESTNUM,5
82 bne a1,a2,fail
83
84 TEST_PASSFAIL
85
86 RVTEST_CODE_END
87
88 .data
89 RVTEST_DATA_BEGIN
90
91 TEST_DATA
92
93 src1:
94 .dword 1
95 .dword 2
96 .dword 3
97 .dword 4
98 src2:
99 .dword 4
100 .dword 3
101 .dword 2
102 .dword 1
103 dest:
104 .dword 0xdeadbeefcafebabe
105 .dword 0xdeadbeefcafebabe
106 .dword 0xdeadbeefcafebabe
107 .dword 0xdeadbeefcafebabe
108
109 RVTEST_DATA_END