cddae2934b0a7d32be03d5541b260572c7fa2d1c
[riscv-tests.git] / isa / rv64sv / illegal_inst.S
1 #*****************************************************************************
2 # illegal_tvec_cmd.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal tvec command trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EI # enable interrupt
15
16 la a3,handler
17 mtpcr a3,evec # set exception handler
18
19 mfpcr a3,status
20 li a4,(1 << IRQ_COP)
21 slli a4,a4,SR_IM_SHIFT
22 or a3,a3,a4 # enable IM[COP]
23 mtpcr a3,status
24
25 .word 0xff00002b
26
27 vsetcfg 32,0
28 li a3,4
29 vsetvl a3,a3
30
31 vtcode1:
32 lw x2, 0(x1)
33 stop
34
35 vtcode2:
36 add x2,x2,x3
37 stop
38
39 handler:
40 vxcptkill
41
42 li x28,2
43
44 # check cause
45 vxcptcause a3
46 li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION
47 bne a3,a4,fail
48
49 # check vec irq aux
50 vxcptaux a3
51 li a4, 0xff00002b
52 bne a3,a4,fail
53
54 # make sure vector unit has cleared out
55 vsetcfg 32,0
56 li a3,4
57 vsetvl a3,a3
58
59 la a3,src1
60 la a4,src2
61 vld vx2,a3
62 vld vx3,a4
63 lui a0,%hi(vtcode2)
64 vf %lo(vtcode2)(a0)
65 la a5,dest
66 vsd vx2,a5
67 fence
68
69 ld a1,0(a5)
70 li a2,5
71 li x28,2
72 bne a1,a2,fail
73 ld a1,8(a5)
74 li x28,3
75 bne a1,a2,fail
76 ld a1,16(a5)
77 li x28,4
78 bne a1,a2,fail
79 ld a1,24(a5)
80 li x28,5
81 bne a1,a2,fail
82
83 TEST_PASSFAIL
84
85 RVTEST_CODE_END
86
87 .data
88 RVTEST_DATA_BEGIN
89
90 TEST_DATA
91
92 src1:
93 .dword 1
94 .dword 2
95 .dword 3
96 .dword 4
97 src2:
98 .dword 4
99 .dword 3
100 .dword 2
101 .dword 1
102 dest:
103 .dword 0xdeadbeefcafebabe
104 .dword 0xdeadbeefcafebabe
105 .dword 0xdeadbeefcafebabe
106 .dword 0xdeadbeefcafebabe
107
108 RVTEST_DATA_END