disable vector bank tests
[riscv-tests.git] / isa / rv64sv / illegal_tvec_cmd.S
1 #*****************************************************************************
2 # illegal_tvec_cmd.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal tvec command trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 mfpcr a3,cr0
15 li a4,1
16 slli a5,a4,8
17 or a3,a3,a4 # enable traps
18 mtpcr a3,cr0
19
20 la a3,handler
21 mtpcr a3,cr3 # set exception handler
22
23 vsetcfg 32,0
24 li a3,4
25 vsetvl a3,a3
26
27 la a3, dest+1
28 vmsv vx1, a3
29 addi a3, x0, 0x1
30 sll a3, a3, 12
31 venqcmd a3, x0
32 lui a0,%hi(vtcode1)
33 vf %lo(vtcode1)(a0)
34 fence
35
36 vtcode1:
37 lw x2, 0(x1)
38 stop
39
40 vtcode2:
41 add x2,x2,x3
42 stop
43
44 handler:
45 vxcptkill
46
47 li x28,2
48
49 # check cause
50 mfpcr a3,cr6
51 li a4,27
52 bne a3,a4,fail
53
54 # check vec irq aux
55 mfpcr a3,cr2
56 addi a4, x0, 0x1
57 sll a4, a4, 12
58 bne a3,a4,fail
59
60 # make sure vector unit has cleared out
61 vsetcfg 32,0
62 li a3,4
63 vsetvl a3,a3
64
65 la a3,src1
66 la a4,src2
67 vld vx2,a3
68 vld vx3,a4
69 lui a0,%hi(vtcode2)
70 vf %lo(vtcode2)(a0)
71 la a5,dest
72 vsd vx2,a5
73 fence
74
75 ld a1,0(a5)
76 li a2,5
77 li x28,2
78 bne a1,a2,fail
79 ld a1,8(a5)
80 li x28,3
81 bne a1,a2,fail
82 ld a1,16(a5)
83 li x28,4
84 bne a1,a2,fail
85 ld a1,24(a5)
86 li x28,5
87 bne a1,a2,fail
88
89 TEST_PASSFAIL
90
91 RVTEST_CODE_END
92
93 .data
94 RVTEST_DATA_BEGIN
95
96 TEST_DATA
97
98 src1:
99 .dword 1
100 .dword 2
101 .dword 3
102 .dword 4
103 src2:
104 .dword 4
105 .dword 3
106 .dword 2
107 .dword 1
108 dest:
109 .dword 0xdeadbeefcafebabe
110 .dword 0xdeadbeefcafebabe
111 .dword 0xdeadbeefcafebabe
112 .dword 0xdeadbeefcafebabe
113
114 RVTEST_DATA_END