Add another FP recoding test case
[riscv-tests.git] / isa / rv64sv / illegal_tvec_regid.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal_tvec_regid.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal tvec regid trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
17 TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)
18
19 TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2)
20 TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2)
21
22 TEST_PASSFAIL
23
24 # the handler gets rewritten for every test, but need this for the framework
25 stvec_handler:
26 j fail
27
28 RVTEST_CODE_END
29
30 .data
31 RVTEST_DATA_BEGIN
32
33 TEST_DATA
34
35 src1:
36 .dword 1
37 .dword 2
38 .dword 3
39 .dword 4
40 src2:
41 .dword 4
42 .dword 3
43 .dword 2
44 .dword 1
45 dest:
46 .dword 0xdeadbeefcafebabe
47 .dword 0xdeadbeefcafebabe
48 .dword 0xdeadbeefcafebabe
49 .dword 0xdeadbeefcafebabe
50
51 RVTEST_DATA_END