correctly set SR_EA bit for all vector physical supervisor tests
[riscv-tests.git] / isa / rv64sv / illegal_tvec_regid.S
1 #*****************************************************************************
2 # illegal_tvec_regid.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal tvec regid trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EA # enable accelerator
15
16 mfpcr a3,status
17 li a4,(1 << IRQ_COP)
18 slli a4,a4,SR_IM_SHIFT
19 or a3,a3,a4 # enable IM[COP]
20 mtpcr a3,status
21
22 TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
23 TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)
24
25 TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2)
26 TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2)
27
28 TEST_PASSFAIL
29
30 RVTEST_CODE_END
31
32 .data
33 RVTEST_DATA_BEGIN
34
35 TEST_DATA
36
37 src1:
38 .dword 1
39 .dword 2
40 .dword 3
41 .dword 4
42 src2:
43 .dword 4
44 .dword 3
45 .dword 2
46 .dword 1
47 dest:
48 .dword 0xdeadbeefcafebabe
49 .dword 0xdeadbeefcafebabe
50 .dword 0xdeadbeefcafebabe
51 .dword 0xdeadbeefcafebabe
52
53 RVTEST_DATA_END