d57aecae0b6849ed6b543c7e62b5b553f5134fa3
[riscv-tests.git] / isa / rv64sv / illegal_tvec_regid.S
1 #*****************************************************************************
2 # illegal_tvec_regid.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal tvec regid trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 mfpcr a3,status
15 li a4,(1 << IRQ_COP)
16 slli a4,a4,SR_IM_SHIFT
17 or a3,a3,a4 # enable IM[COP]
18 mtpcr a3,status
19
20 TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
21 TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)
22
23 TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2)
24 TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2)
25
26 TEST_PASSFAIL
27
28 RVTEST_CODE_END
29
30 .data
31 RVTEST_DATA_BEGIN
32
33 TEST_DATA
34
35 src1:
36 .dword 1
37 .dword 2
38 .dword 3
39 .dword 4
40 src2:
41 .dword 4
42 .dword 3
43 .dword 2
44 .dword 1
45 dest:
46 .dword 0xdeadbeefcafebabe
47 .dword 0xdeadbeefcafebabe
48 .dword 0xdeadbeefcafebabe
49 .dword 0xdeadbeefcafebabe
50
51 RVTEST_DATA_END