initial commit
[riscv-tests.git] / isa / rv64sv / illegal_vt_inst.S
1 #*****************************************************************************
2 # illegal_vt_inst.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal vt instruction trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 mfpcr a3,cr0
15 li a4,1
16 slli a5,a4,8
17 or a3,a3,a4 # enable traps
18 mtpcr a3,cr0
19
20 la a3,handler
21 mtpcr a3,cr3 # set exception handler
22
23 li a3,4
24 vvcfgivl a3,a3,32,0
25
26 la a3,src1
27 la a4,src2
28 vld vx2,a3
29 vld vx3,a4
30 lui a0,%hi(vtcode1)
31 vf %lo(vtcode1)(a0)
32 fence.v.l
33
34 vtcode1:
35 add x2,x2,x3
36 illegal:
37 .word 0x0
38 stop
39
40 vtcode2:
41 add x2,x2,x3
42 stop
43
44 handler:
45 vxcptkill
46
47 li x28,2
48
49 # check cause
50 mfpcr a3,cr6
51 li a4,26
52 bne a3,a4,fail
53
54 # check badvaddr
55 mfpcr a3,cr2
56 la a4,illegal
57 bne a3,a4,fail
58
59 # make sure vector unit has cleared out
60 li a3,4
61 vvcfgivl a3,a3,32,0
62
63 la a3,src1
64 la a4,src2
65 vld vx2,a3
66 vld vx3,a4
67 lui a0,%hi(vtcode2)
68 vf %lo(vtcode2)(a0)
69 la a5,dest
70 vsd vx2,a5
71 fence.v.l
72
73 ld a1,0(a5)
74 li a2,5
75 li x28,2
76 bne a1,a2,fail
77 ld a1,8(a5)
78 li x28,3
79 bne a1,a2,fail
80 ld a1,16(a5)
81 li x28,4
82 bne a1,a2,fail
83 ld a1,24(a5)
84 li x28,5
85 bne a1,a2,fail
86
87 TEST_PASSFAIL
88
89 RVTEST_CODE_END
90
91 .data
92 RVTEST_DATA_BEGIN
93
94 TEST_DATA
95
96 src1:
97 .dword 1
98 .dword 2
99 .dword 3
100 .dword 4
101 src2:
102 .dword 4
103 .dword 3
104 .dword 2
105 .dword 1
106 dest:
107 .dword 0xdeadbeefcafebabe
108 .dword 0xdeadbeefcafebabe
109 .dword 0xdeadbeefcafebabe
110 .dword 0xdeadbeefcafebabe
111
112 RVTEST_DATA_END