correctly set SR_EA bit for all vector physical supervisor tests
[riscv-tests.git] / isa / rv64sv / illegal_vt_regid.S
1 #*****************************************************************************
2 # xcpt_illegal_vt_regid.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test illegal vt regid trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EA # enable accelerator
15
16 mfpcr a3,status
17 li a4,(1 << IRQ_COP)
18 slli a4,a4,SR_IM_SHIFT
19 or a3,a3,a4 # enable IM[COP]
20 mtpcr a3,status
21
22 TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
23 TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)
24 TEST_ILLEGAL_VT_REGID(4, 5, 5, add, x1, x2, x7)
25
26 TEST_ILLEGAL_VT_REGID(5, 5, 5, fadd.d, f7, f1, f2)
27 TEST_ILLEGAL_VT_REGID(6, 5, 5, fadd.d, f1, f7, f2)
28 TEST_ILLEGAL_VT_REGID(7, 5, 5, fadd.d, f1, f2, f7)
29
30 TEST_PASSFAIL
31
32 RVTEST_CODE_END
33
34 .data
35 RVTEST_DATA_BEGIN
36
37 TEST_DATA
38
39 src1:
40 .dword 1
41 .dword 2
42 .dword 3
43 .dword 4
44 src2:
45 .dword 4
46 .dword 3
47 .dword 2
48 .dword 1
49 dest:
50 .dword 0xdeadbeefcafebabe
51 .dword 0xdeadbeefcafebabe
52 .dword 0xdeadbeefcafebabe
53 .dword 0xdeadbeefcafebabe
54
55 RVTEST_DATA_END