2cc42bce7bf53ca60351ac4393f6f910f85c4a5e
[riscv-tests.git] / isa / rv64sv / ma_utld.S
1 #*****************************************************************************
2 # ma_utld.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test misaligned ut ld trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EI # enable interrupt
15
16 la a3,handler
17 mtpcr a3,evec # set exception handler
18
19 mfpcr a3,status
20 li a4,(1 << IRQ_COP)
21 slli a4,a4,SR_IM_SHIFT
22 or a3,a3,a4 # enable IM[COP]
23 mtpcr a3,status
24
25 vsetcfg 32,0
26 li a3,4
27 vsetvl a3,a3
28
29 la a3, dest+1
30 vmsv vx1, a3
31 lui a0,%hi(vtcode1)
32 vf %lo(vtcode1)(a0)
33 fence
34
35 vtcode1:
36 lw x2, 0(x1)
37 stop
38
39 vtcode2:
40 add x2,x2,x3
41 stop
42
43 handler:
44 vxcptkill
45
46 li x28,2
47
48 # check cause
49 vxcptcause a3
50 li a4,HWACHA_CAUSE_MISALIGNED_LOAD
51 bne a3,a4,fail
52
53 # check vec irq aux
54 vxcptaux a3
55 la a4,dest+1
56 bne a3,a4,fail
57
58 # make sure vector unit has cleared out
59 vsetcfg 32,0
60 li a3,4
61 vsetvl a3,a3
62
63 la a3,src1
64 la a4,src2
65 vld vx2,a3
66 vld vx3,a4
67 lui a0,%hi(vtcode2)
68 vf %lo(vtcode2)(a0)
69 la a5,dest
70 vsd vx2,a5
71 fence
72
73 ld a1,0(a5)
74 li a2,5
75 li x28,2
76 bne a1,a2,fail
77 ld a1,8(a5)
78 li x28,3
79 bne a1,a2,fail
80 ld a1,16(a5)
81 li x28,4
82 bne a1,a2,fail
83 ld a1,24(a5)
84 li x28,5
85 bne a1,a2,fail
86
87 TEST_PASSFAIL
88
89 RVTEST_CODE_END
90
91 .data
92 RVTEST_DATA_BEGIN
93
94 TEST_DATA
95
96 src1:
97 .dword 1
98 .dword 2
99 .dword 3
100 .dword 4
101 src2:
102 .dword 4
103 .dword 3
104 .dword 2
105 .dword 1
106 dest:
107 .dword 0xdeadbeefcafebabe
108 .dword 0xdeadbeefcafebabe
109 .dword 0xdeadbeefcafebabe
110 .dword 0xdeadbeefcafebabe
111
112 RVTEST_DATA_END