isa/rv64sv/ma_utld.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_utld.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ut ld trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64SV
  14 RVTEST_CODE_BEGIN
  15
  16   la a3,handler
  17   csrw stvec,a3 # set exception handler
  18
  19   vsetcfg 32,0
  20   li a3,4
  21   vsetvl a3,a3
  22
  23   la a3, dest+1
  24   vmsv vx1, a3
  25   lui a0,%hi(vtcode1)
  26   vf %lo(vtcode1)(a0)
  27   fence
  28
  29 vtcode1:
  30   lw x2, 0(x1)
  31   stop
  32
  33 vtcode2:
  34   add x2,x2,x3
  35   stop
  36
  37 handler:
  38   vxcptkill
  39
  40   li TESTNUM,2
  41
  42   # check cause
  43   vxcptcause a3
  44   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
  45   bne a3,a4,fail
  46
  47   # check vec irq aux
  48   vxcptaux a3
  49   la a4,dest+1
  50   bne a3,a4,fail
  51
  52   # make sure vector unit has cleared out
  53   vsetcfg 32,0
  54   li a3,4
  55   vsetvl a3,a3
  56
  57   la a3,src1
  58   la a4,src2
  59   vld vx2,a3
  60   vld vx3,a4
  61   lui a0,%hi(vtcode2)
  62   vf %lo(vtcode2)(a0)
  63   la a5,dest
  64   vsd vx2,a5
  65   fence
  66
  67   ld a1,0(a5)
  68   li a2,5
  69   li TESTNUM,2
  70   bne a1,a2,fail
  71   ld a1,8(a5)
  72   li TESTNUM,3
  73   bne a1,a2,fail
  74   ld a1,16(a5)
  75   li TESTNUM,4
  76   bne a1,a2,fail
  77   ld a1,24(a5)
  78   li TESTNUM,5
  79   bne a1,a2,fail
  80
  81   TEST_PASSFAIL
  82
  83 RVTEST_CODE_END
  84
  85   .data
  86 RVTEST_DATA_BEGIN
  87
  88   TEST_DATA
  89
  90 src1:
  91   .dword 1
  92   .dword 2
  93   .dword 3
  94   .dword 4
  95 src2:
  96   .dword 4
  97   .dword 3
  98   .dword 2
  99   .dword 1
 100 dest:
 101   .dword 0xdeadbeefcafebabe
 102   .dword 0xdeadbeefcafebabe
 103   .dword 0xdeadbeefcafebabe
 104   .dword 0xdeadbeefcafebabe
 105
 106 RVTEST_DATA_END