3bd74370c98eed8026981c98401dae7161eed119
[riscv-tests.git] / isa / rv64sv / ma_utld.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ma_utld.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test misaligned ut ld trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 li a0, SR_EA | SR_EI
17 csrs status, a0
18
19 la a3,handler
20 csrw evec,a3 # set exception handler
21
22 csrr a3,status
23 li a4,(1 << IRQ_COP)
24 slli a4,a4,SR_IM_SHIFT
25 or a3,a3,a4 # enable IM[COP]
26 csrw status,a3
27
28 vsetcfg 32,0
29 li a3,4
30 vsetvl a3,a3
31
32 la a3, dest+1
33 vmsv vx1, a3
34 lui a0,%hi(vtcode1)
35 vf %lo(vtcode1)(a0)
36 fence
37
38 vtcode1:
39 lw x2, 0(x1)
40 stop
41
42 vtcode2:
43 add x2,x2,x3
44 stop
45
46 handler:
47 vxcptkill
48
49 li TESTNUM,2
50
51 # check cause
52 vxcptcause a3
53 li a4,HWACHA_CAUSE_MISALIGNED_LOAD
54 bne a3,a4,fail
55
56 # check vec irq aux
57 vxcptaux a3
58 la a4,dest+1
59 bne a3,a4,fail
60
61 # make sure vector unit has cleared out
62 vsetcfg 32,0
63 li a3,4
64 vsetvl a3,a3
65
66 la a3,src1
67 la a4,src2
68 vld vx2,a3
69 vld vx3,a4
70 lui a0,%hi(vtcode2)
71 vf %lo(vtcode2)(a0)
72 la a5,dest
73 vsd vx2,a5
74 fence
75
76 ld a1,0(a5)
77 li a2,5
78 li TESTNUM,2
79 bne a1,a2,fail
80 ld a1,8(a5)
81 li TESTNUM,3
82 bne a1,a2,fail
83 ld a1,16(a5)
84 li TESTNUM,4
85 bne a1,a2,fail
86 ld a1,24(a5)
87 li TESTNUM,5
88 bne a1,a2,fail
89
90 TEST_PASSFAIL
91
92 RVTEST_CODE_END
93
94 .data
95 RVTEST_DATA_BEGIN
96
97 TEST_DATA
98
99 src1:
100 .dword 1
101 .dword 2
102 .dword 3
103 .dword 4
104 src2:
105 .dword 4
106 .dword 3
107 .dword 2
108 .dword 1
109 dest:
110 .dword 0xdeadbeefcafebabe
111 .dword 0xdeadbeefcafebabe
112 .dword 0xdeadbeefcafebabe
113 .dword 0xdeadbeefcafebabe
114
115 RVTEST_DATA_END