isa/rv64sv/ma_utld.S

   1 #*****************************************************************************
   2 # ma_utld.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test misaligned ut ld trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64S
  12 RVTEST_CODE_BEGIN
  13
  14   mfpcr a3,cr0
  15   li a4,1
  16   slli a5,a4,8
  17   or a3,a3,a4 # enable traps
  18   mtpcr a3,cr0
  19
  20   la a3,handler
  21   mtpcr a3,cr3 # set exception handler
  22
  23   li a3,4
  24   vvcfgivl a3,a3,32,0
  25
  26   la a3, dest+1
  27   vmsv vx1, a3
  28   lui a0,%hi(vtcode1)
  29   vf %lo(vtcode1)(a0)
  30   fence.v.l
  31
  32 vtcode1:
  33   lw x2, 0(x1)
  34   stop
  35
  36 vtcode2:
  37   add x2,x2,x3
  38   stop
  39
  40 handler:
  41   vxcptkill
  42
  43   li x28,2
  44
  45   # check cause
  46   mfpcr a3,cr6
  47   li a4,28
  48   bne a3,a4,fail
  49
  50   # check vec irq aux
  51   mfpcr a3,cr2
  52   la a4,dest+1
  53   bne a3,a4,fail
  54
  55   # make sure vector unit has cleared out
  56   li a3,4
  57   vvcfgivl a3,a3,32,0
  58
  59   la a3,src1
  60   la a4,src2
  61   vld vx2,a3
  62   vld vx3,a4
  63   lui a0,%hi(vtcode2)
  64   vf %lo(vtcode2)(a0)
  65   la a5,dest
  66   vsd vx2,a5
  67   fence.v.l
  68
  69   ld a1,0(a5)
  70   li a2,5
  71   li x28,2
  72   bne a1,a2,fail
  73   ld a1,8(a5)
  74   li x28,3
  75   bne a1,a2,fail
  76   ld a1,16(a5)
  77   li x28,4
  78   bne a1,a2,fail
  79   ld a1,24(a5)
  80   li x28,5
  81   bne a1,a2,fail
  82
  83   TEST_PASSFAIL
  84
  85 RVTEST_CODE_END
  86
  87   .data
  88 RVTEST_DATA_BEGIN
  89
  90   TEST_DATA
  91
  92 src1:
  93   .dword 1
  94   .dword 2
  95   .dword 3
  96   .dword 4
  97 src2:
  98   .dword 4
  99   .dword 3
 100   .dword 2
 101   .dword 1
 102 dest:
 103   .dword 0xdeadbeefcafebabe
 104   .dword 0xdeadbeefcafebabe
 105   .dword 0xdeadbeefcafebabe
 106   .dword 0xdeadbeefcafebabe
 107
 108 RVTEST_DATA_END