isa/rv64sv/ma_utsd.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_utsd.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ut sd trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64SV
  14 RVTEST_CODE_BEGIN
  15
  16   vsetcfg 32,0
  17   li a3,4
  18   vsetvl a3,a3
  19
  20   la a3, dest+1
  21   vmsv vx1, a3
  22   lui a0,%hi(vtcode1)
  23   vf %lo(vtcode1)(a0)
  24   la a3, dest+1
  25   vsd vx1, a3
  26   fence
  27
  28 vtcode1:
  29   sw x2, 0(x1)
  30   stop
  31
  32 vtcode2:
  33   add x2,x2,x3
  34   stop
  35
  36 stvec_handler:
  37   vxcptkill
  38
  39   li TESTNUM,2
  40
  41   # check cause
  42   csrr a3, scause
  43   li a4,HWACHA_CAUSE_MISALIGNED_STORE
  44   bne a3,a4,fail
  45
  46   # check vec irq aux
  47   csrr a3, sbadaddr
  48   la a4, dest+1
  49   bne a3,a4,fail
  50
  51   # make sure vector unit has cleared out
  52   vsetcfg 32,0
  53   li a3,4
  54   vsetvl a3,a3
  55
  56   la a3,src1
  57   la a4,src2
  58   vld vx2,a3
  59   vld vx3,a4
  60   lui a0,%hi(vtcode2)
  61   vf %lo(vtcode2)(a0)
  62   la a5,dest
  63   vsd vx2,a5
  64   fence
  65
  66   ld a1,0(a5)
  67   li a2,5
  68   li TESTNUM,2
  69   bne a1,a2,fail
  70   ld a1,8(a5)
  71   li TESTNUM,3
  72   bne a1,a2,fail
  73   ld a1,16(a5)
  74   li TESTNUM,4
  75   bne a1,a2,fail
  76   ld a1,24(a5)
  77   li TESTNUM,5
  78   bne a1,a2,fail
  79
  80   TEST_PASSFAIL
  81
  82 RVTEST_CODE_END
  83
  84   .data
  85 RVTEST_DATA_BEGIN
  86
  87   TEST_DATA
  88
  89 src1:
  90   .dword 1
  91   .dword 2
  92   .dword 3
  93   .dword 4
  94 src2:
  95   .dword 4
  96   .dword 3
  97   .dword 2
  98   .dword 1
  99 dest:
 100   .dword 0xdeadbeefcafebabe
 101   .dword 0xdeadbeefcafebabe
 102   .dword 0xdeadbeefcafebabe
 103   .dword 0xdeadbeefcafebabe
 104
 105 RVTEST_DATA_END