initial commit
[riscv-tests.git] / isa / rv64sv / ma_utsd.S
1 #*****************************************************************************
2 # ma_utsd.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test misaligned ut sd trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 mfpcr a3,cr0
15 li a4,1
16 slli a5,a4,8
17 or a3,a3,a4 # enable traps
18 mtpcr a3,cr0
19
20 la a3,handler
21 mtpcr a3,cr3 # set exception handler
22
23 li a3,4
24 vvcfgivl a3,a3,32,0
25
26 la a3, dest+1
27 vmsv vx1, a3
28 lui a0,%hi(vtcode1)
29 vf %lo(vtcode1)(a0)
30 la a3, dest+1
31 vsd vx1, a3
32 fence.v.l
33
34 vtcode1:
35 sw x2, 0(x1)
36 stop
37
38 vtcode2:
39 add x2,x2,x3
40 stop
41
42 handler:
43 vxcptkill
44
45 li x28,2
46
47 # check cause
48 mfpcr a3,cr6
49 li a4,29
50 bne a3,a4,fail
51
52 # check vec irq aux
53 mfpcr a3,cr2
54 la a4, dest+1
55 bne a3,a4,fail
56
57 # make sure vector unit has cleared out
58 li a3,4
59 vvcfgivl a3,a3,32,0
60
61 la a3,src1
62 la a4,src2
63 vld vx2,a3
64 vld vx3,a4
65 lui a0,%hi(vtcode2)
66 vf %lo(vtcode2)(a0)
67 la a5,dest
68 vsd vx2,a5
69 fence.v.l
70
71 ld a1,0(a5)
72 li a2,5
73 li x28,2
74 bne a1,a2,fail
75 ld a1,8(a5)
76 li x28,3
77 bne a1,a2,fail
78 ld a1,16(a5)
79 li x28,4
80 bne a1,a2,fail
81 ld a1,24(a5)
82 li x28,5
83 bne a1,a2,fail
84
85 TEST_PASSFAIL
86
87 RVTEST_CODE_END
88
89 .data
90 RVTEST_DATA_BEGIN
91
92 TEST_DATA
93
94 src1:
95 .dword 1
96 .dword 2
97 .dword 3
98 .dword 4
99 src2:
100 .dword 4
101 .dword 3
102 .dword 2
103 .dword 1
104 dest:
105 .dword 0xdeadbeefcafebabe
106 .dword 0xdeadbeefcafebabe
107 .dword 0xdeadbeefcafebabe
108 .dword 0xdeadbeefcafebabe
109
110 RVTEST_DATA_END