Add LICENSE
[riscv-tests.git] / isa / rv64sv / ma_utsd.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ma_utsd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test misaligned ut sd trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15 li a0, SR_EA | SR_EI
16 csrs status, a0
17
18 la a3,handler
19 csrw evec,a3 # set exception handler
20
21 csrr a3,status
22 li a4,(1 << IRQ_COP)
23 slli a4,a4,SR_IM_SHIFT
24 or a3,a3,a4 # enable IM[COP]
25 csrw status,a3
26
27 vsetcfg 32,0
28 li a3,4
29 vsetvl a3,a3
30
31 la a3, dest+1
32 vmsv vx1, a3
33 lui a0,%hi(vtcode1)
34 vf %lo(vtcode1)(a0)
35 la a3, dest+1
36 vsd vx1, a3
37 fence
38
39 vtcode1:
40 sw x2, 0(x1)
41 stop
42
43 vtcode2:
44 add x2,x2,x3
45 stop
46
47 handler:
48 vxcptkill
49
50 li TESTNUM,2
51
52 # check cause
53 vxcptcause a3
54 li a4,HWACHA_CAUSE_MISALIGNED_STORE
55 bne a3,a4,fail
56
57 # check vec irq aux
58 vxcptaux a3
59 la a4, dest+1
60 bne a3,a4,fail
61
62 # make sure vector unit has cleared out
63 vsetcfg 32,0
64 li a3,4
65 vsetvl a3,a3
66
67 la a3,src1
68 la a4,src2
69 vld vx2,a3
70 vld vx3,a4
71 lui a0,%hi(vtcode2)
72 vf %lo(vtcode2)(a0)
73 la a5,dest
74 vsd vx2,a5
75 fence
76
77 ld a1,0(a5)
78 li a2,5
79 li TESTNUM,2
80 bne a1,a2,fail
81 ld a1,8(a5)
82 li TESTNUM,3
83 bne a1,a2,fail
84 ld a1,16(a5)
85 li TESTNUM,4
86 bne a1,a2,fail
87 ld a1,24(a5)
88 li TESTNUM,5
89 bne a1,a2,fail
90
91 TEST_PASSFAIL
92
93 RVTEST_CODE_END
94
95 .data
96 RVTEST_DATA_BEGIN
97
98 TEST_DATA
99
100 src1:
101 .dword 1
102 .dword 2
103 .dword 3
104 .dword 4
105 src2:
106 .dword 4
107 .dword 3
108 .dword 2
109 .dword 1
110 dest:
111 .dword 0xdeadbeefcafebabe
112 .dword 0xdeadbeefcafebabe
113 .dword 0xdeadbeefcafebabe
114 .dword 0xdeadbeefcafebabe
115
116 RVTEST_DATA_END