isa/rv64sv/ma_vld.S

   1 #*****************************************************************************
   2 # ma_vld.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test misaligned vector ld trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64S
  12 RVTEST_CODE_BEGIN
  13
  14   mfpcr a3,cr0
  15   li a4,1
  16   slli a5,a4,8
  17   or a3,a3,a4 # enable traps
  18   mtpcr a3,cr0
  19
  20   la a3,handler
  21   mtpcr a3,cr3 # set exception handler
  22
  23   li a3,4
  24   vvcfgivl a3,a3,32,0
  25
  26   la a3, dest+1
  27   vld vx2,a3
  28   vld vx3,a4
  29   lui a0,%hi(vtcode1)
  30   vf %lo(vtcode1)(a0)
  31   fence.v.l
  32
  33 vtcode1:
  34   add x2,x2,x3
  35   stop
  36
  37 vtcode2:
  38   add x2,x2,x3
  39   stop
  40
  41 handler:
  42   vxcptkill
  43
  44   li x28,2
  45
  46   # check cause
  47   mfpcr a3,cr6
  48   li a4,28
  49   bne a3,a4,fail
  50
  51   # check vec irq aux
  52   mfpcr a3,cr2
  53   la a4,dest+1
  54   bne a3,a4,fail
  55
  56   # make sure vector unit has cleared out
  57   li a3,4
  58   vvcfgivl a3,a3,32,0
  59
  60   la a3,src1
  61   la a4,src2
  62   vld vx2,a3
  63   vld vx3,a4
  64   lui a0,%hi(vtcode2)
  65   vf %lo(vtcode2)(a0)
  66   la a5,dest
  67   vsd vx2,a5
  68   fence.v.l
  69
  70   ld a1,0(a5)
  71   li a2,5
  72   li x28,2
  73   bne a1,a2,fail
  74   ld a1,8(a5)
  75   li x28,3
  76   bne a1,a2,fail
  77   ld a1,16(a5)
  78   li x28,4
  79   bne a1,a2,fail
  80   ld a1,24(a5)
  81   li x28,5
  82   bne a1,a2,fail
  83
  84   TEST_PASSFAIL
  85
  86 RVTEST_CODE_END
  87
  88   .data
  89 RVTEST_DATA_BEGIN
  90
  91   TEST_DATA
  92
  93 src1:
  94   .dword 1
  95   .dword 2
  96   .dword 3
  97   .dword 4
  98 src2:
  99   .dword 4
 100   .dword 3
 101   .dword 2
 102   .dword 1
 103 dest:
 104   .dword 0xdeadbeefcafebabe
 105   .dword 0xdeadbeefcafebabe
 106   .dword 0xdeadbeefcafebabe
 107   .dword 0xdeadbeefcafebabe
 108
 109 RVTEST_DATA_END