add hwacha exception support
[riscv-tests.git] / isa / rv64sv / ma_vld.S
1 #*****************************************************************************
2 # ma_vld.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test misaligned vector ld trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EI # enable interrupt
15
16 la a3,handler
17 mtpcr a3,evec # set exception handler
18
19 mfpcr a3,status
20 li a4,(1 << IRQ_COP)
21 slli a4,a4,SR_IM_SHIFT
22 or a3,a3,a4 # enable IM[COP]
23 mtpcr a3,status
24
25 vsetcfg 32,0
26 li a3,4
27 vsetvl a3,a3
28
29 la a3, dest+1
30 vld vx2,a3
31 vld vx3,a4
32 lui a0,%hi(vtcode1)
33 vf %lo(vtcode1)(a0)
34 fence
35
36 vtcode1:
37 add x2,x2,x3
38 stop
39
40 vtcode2:
41 add x2,x2,x3
42 stop
43
44 handler:
45 vxcptkill
46
47 li x28,2
48
49 # check cause
50 vxcptcause a3
51 li a4,HWACHA_CAUSE_MISALIGNED_LOAD
52 bne a3,a4,fail
53
54 # check vec irq aux
55 vxcptaux a3
56 la a4,dest+1
57 bne a3,a4,fail
58
59 # make sure vector unit has cleared out
60 vsetcfg 32,0
61 li a3,4
62 vsetvl a3,a3
63
64 la a3,src1
65 la a4,src2
66 vld vx2,a3
67 vld vx3,a4
68 lui a0,%hi(vtcode2)
69 vf %lo(vtcode2)(a0)
70 la a5,dest
71 vsd vx2,a5
72 fence
73
74 ld a1,0(a5)
75 li a2,5
76 li x28,2
77 bne a1,a2,fail
78 ld a1,8(a5)
79 li x28,3
80 bne a1,a2,fail
81 ld a1,16(a5)
82 li x28,4
83 bne a1,a2,fail
84 ld a1,24(a5)
85 li x28,5
86 bne a1,a2,fail
87
88 TEST_PASSFAIL
89
90 RVTEST_CODE_END
91
92 .data
93 RVTEST_DATA_BEGIN
94
95 TEST_DATA
96
97 src1:
98 .dword 1
99 .dword 2
100 .dword 3
101 .dword 4
102 src2:
103 .dword 4
104 .dword 3
105 .dword 2
106 .dword 1
107 dest:
108 .dword 0xdeadbeefcafebabe
109 .dword 0xdeadbeefcafebabe
110 .dword 0xdeadbeefcafebabe
111 .dword 0xdeadbeefcafebabe
112
113 RVTEST_DATA_END