2271e8f6c8673415526015ab4a550837b165c56a
[riscv-tests.git] / isa / rv64sv / ma_vsd.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ma_vsd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test misaligned vector sd trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 la a3,handler
17 csrw stvec,a3 # set exception handler
18
19 vsetcfg 32,0
20 li a3,4
21 vsetvl a3,a3
22
23 la a3, src1
24 la a4, src2
25 vld vx2,a3
26 vld vx3,a4
27 lui a0,%hi(vtcode1)
28 vf %lo(vtcode1)(a0)
29 la a3, dest+1
30 vsd vx1, a3
31 fence
32
33 vtcode1:
34 add x2,x2,x3
35 stop
36
37 vtcode2:
38 add x2,x2,x3
39 stop
40
41 handler:
42 vxcptkill
43
44 li TESTNUM,2
45
46 # check cause
47 vxcptcause a3
48 li a4,HWACHA_CAUSE_MISALIGNED_STORE
49 bne a3,a4,fail
50
51 # check vec irq aux
52 vxcptaux a3
53 la a4,dest+1
54 bne a3,a4,fail
55
56 # make sure vector unit has cleared out
57 vsetcfg 32,0
58 li a3,4
59 vsetvl a3,a3
60
61 la a3,src1
62 la a4,src2
63 vld vx2,a3
64 vld vx3,a4
65 lui a0,%hi(vtcode2)
66 vf %lo(vtcode2)(a0)
67 la a5,dest
68 vsd vx2,a5
69 fence
70
71 ld a1,0(a5)
72 li a2,5
73 li TESTNUM,2
74 bne a1,a2,fail
75 ld a1,8(a5)
76 li TESTNUM,3
77 bne a1,a2,fail
78 ld a1,16(a5)
79 li TESTNUM,4
80 bne a1,a2,fail
81 ld a1,24(a5)
82 li TESTNUM,5
83 bne a1,a2,fail
84
85 TEST_PASSFAIL
86
87 RVTEST_CODE_END
88
89 .data
90 RVTEST_DATA_BEGIN
91
92 TEST_DATA
93
94 src1:
95 .dword 1
96 .dword 2
97 .dword 3
98 .dword 4
99 src2:
100 .dword 4
101 .dword 3
102 .dword 2
103 .dword 1
104 dest:
105 .dword 0xdeadbeefcafebabe
106 .dword 0xdeadbeefcafebabe
107 .dword 0xdeadbeefcafebabe
108 .dword 0xdeadbeefcafebabe
109
110 RVTEST_DATA_END